adapt to litedram changes
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@ -12,7 +12,8 @@ from litex.soc.integration.builder import *
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from litex.soc.cores import uart
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from litex.soc.integration.soc_core import mem_decoder
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from litedram.modules import PhySettings, IS42S16160
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from litedram.common import PhySettings
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from litedram.modules import IS42S16160
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from litedram.phy.model import SDRAMPHYModel
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from liteeth.phy.model import LiteEthPHYModel
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@ -14,7 +14,7 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
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class ControllerInjector(Module, AutoCSR):
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def __init__(self, phy, geom_settings, timing_settings, controller_settings):
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def __init__(self, phy, geom_settings, timing_settings, **kwargs):
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self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
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phy.settings.dfi_databits, phy.settings.nphases)
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self.comb += self.dfii.master.connect(phy.dfi)
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@ -22,7 +22,7 @@ class ControllerInjector(Module, AutoCSR):
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self.submodules.controller = controller = core.LiteDRAMController(phy.settings,
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geom_settings,
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timing_settings,
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controller_settings)
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**kwargs)
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self.comb += controller.dfi.connect(self.dfii.slave)
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self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits)
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@ -48,14 +48,14 @@ class SoCSDRAM(SoCCore):
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raise FinalizeError
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self._wb_sdram_ifs.append(interface)
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def register_sdram(self, phy, geom_settings, timing_settings, controller_settings=None):
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def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
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assert not self._sdram_phy
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self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
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self.submodules.sdram = ControllerInjector(phy,
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geom_settings,
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timing_settings,
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controller_settings)
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**kwargs)
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dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
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sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
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