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soc/add_sdram: Introduce data_width_ratio and fix id_width in UpConvert case.

This commit is contained in:
Florent Kermarrec 2022-02-18 11:34:08 +01:00
parent 51d952c2d3
commit 55d9b3a403
1 changed files with 7 additions and 3 deletions
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10
litex/soc/integration/soc.py
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@ -1356,16 +1356,20 @@ class LiteXSoC(SoC):
# Check if bus is an AXI bus and connect it. # Check if bus is an AXI bus and connect it.
if isinstance(mem_bus, axi.AXIInterface): if isinstance(mem_bus, axi.AXIInterface):
data_width_ratio = int(port.data_width/mem_bus.data_width)
# If same data_width, connect it directly. # If same data_width, connect it directly.
if port.data_width == mem_bus.data_width: if data_width_ratio == 1:
self.submodules += LiteDRAMAXI2Native( self.submodules += LiteDRAMAXI2Native(
axi = mem_bus, axi = mem_bus,
port = port, port = port,
base_address = self.bus.regions["main_ram"].origin base_address = self.bus.regions["main_ram"].origin
) )
# UpConvert. # UpConvert.
elif port.data_width > mem_bus.data_width: elif data_width_ratio > 1:
axi_port = axi.AXIInterface(data_width=port.data_width, id_width=8) # FIXME: id_width. axi_port = axi.AXIInterface(
data_width = port.data_width,
id_width = len(mem_bus.aw.id),
)
self.submodules += axi.AXIUpConverter( self.submodules += axi.AXIUpConverter(
axi_from = mem_bus, axi_from = mem_bus,
axi_to = axi_port, axi_to = axi_port,