soc/add_sdram: Introduce data_width_ratio and fix id_width in UpConvert case.
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@ -1356,16 +1356,20 @@ class LiteXSoC(SoC):
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# Check if bus is an AXI bus and connect it.
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if isinstance(mem_bus, axi.AXIInterface):
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data_width_ratio = int(port.data_width/mem_bus.data_width)
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# If same data_width, connect it directly.
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if port.data_width == mem_bus.data_width:
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if data_width_ratio == 1:
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self.submodules += LiteDRAMAXI2Native(
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axi = mem_bus,
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port = port,
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base_address = self.bus.regions["main_ram"].origin
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)
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# UpConvert.
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elif port.data_width > mem_bus.data_width:
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axi_port = axi.AXIInterface(data_width=port.data_width, id_width=8) # FIXME: id_width.
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elif data_width_ratio > 1:
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axi_port = axi.AXIInterface(
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data_width = port.data_width,
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id_width = len(mem_bus.aw.id),
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)
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self.submodules += axi.AXIUpConverter(
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axi_from = mem_bus,
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axi_to = axi_port,
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