Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #60 from q3k/for-upstream/top-level-module-selection 

Top module selection (for Verilator and Diamond)
This commit is contained in:
enjoy-digital 2018-02-19 12:27:25 +01:00 committed by GitHub
parent 7b5bd4041a ef511e7edc
commit 55fc9d2d6b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
litex/build/lattice/diamond.py
View File

@ -52,6 +52,7 @@ def _build_files(device, sources, vincpaths, build_name):
tcl.append("prj_impl option {include path} {\"" + path + "\"}") tcl.append("prj_impl option {include path} {\"" + path + "\"}")
for filename, language, library in sources: for filename, language, library in sources:
tcl.append("prj_src add \"" + filename + "\" -work " + library) tcl.append("prj_src add \"" + filename + "\" -work " + library)
tcl.append("prj_impl option top \"{}\"".format(build_name))
tcl.append("prj_run Synthesis -impl implementation -forceOne") tcl.append("prj_run Synthesis -impl implementation -forceOne")
tcl.append("prj_run Translate -impl implementation") tcl.append("prj_run Translate -impl implementation")
tcl.append("prj_run Map -impl implementation") tcl.append("prj_run Map -impl implementation")

1
litex/build/sim/core/Makefile
View File

@ -26,6 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
sim: mkdir $(OBJS_SIM) sim: mkdir $(OBJS_SIM)
verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \ verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
$(SRCS_SIM_CPP) $(OBJS_SIM) \ $(SRCS_SIM_CPP) $(OBJS_SIM) \
--top-module dut \
-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
-LDFLAGS "$(LDFLAGS)" \ -LDFLAGS "$(LDFLAGS)" \
-trace $(INC_DIR) -trace $(INC_DIR)