Merge pull request #60 from q3k/for-upstream/top-level-module-selection

Top module selection (for Verilator and Diamond)

litex/build/lattice/diamond.py

@@ -52,6 +52,7 @@ def _build_files(device, sources, vincpaths, build_name):
         tcl.append("prj_impl option {include path} {\"" + path + "\"}")
     for filename, language, library in sources:
         tcl.append("prj_src add \"" + filename + "\" -work " + library)
+    tcl.append("prj_impl option top \"{}\"".format(build_name))
     tcl.append("prj_run Synthesis -impl implementation -forceOne")
     tcl.append("prj_run Translate -impl implementation")
     tcl.append("prj_run Map -impl implementation")

litex/build/sim/core/Makefile

@@ -26,6 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
 sim: mkdir $(OBJS_SIM)
 	verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
 		$(SRCS_SIM_CPP) $(OBJS_SIM) \
+		--top-module dut \
 		-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
 		-LDFLAGS "$(LDFLAGS)" \
 		-trace $(INC_DIR)