migen/genlib/cdc: fix BusSynchronizer
ping/pong token can be lost when: - source clock domain starts before destination clock domain. - a clock domain stops. This fix add a timeout to detect such situation and create another token.
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@ -2,6 +2,7 @@ from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Special
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from migen.fhdl.specials import Special
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from migen.fhdl.bitcontainer import value_bits_sign
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from migen.fhdl.bitcontainer import value_bits_sign
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from migen.genlib.misc import WaitTimer
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class NoRetiming(Special):
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class NoRetiming(Special):
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@ -88,7 +89,7 @@ class BusSynchronizer(Module):
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Ensures that all the bits form a single word that was present
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Ensures that all the bits form a single word that was present
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synchronously in the input clock domain (unlike direct use of
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synchronously in the input clock domain (unlike direct use of
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``MultiReg``)."""
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``MultiReg``)."""
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def __init__(self, width, idomain, odomain):
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def __init__(self, width, idomain, odomain, timeout=128):
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self.i = Signal(width)
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self.i = Signal(width)
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self.o = Signal(width)
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self.o = Signal(width)
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@ -102,8 +103,10 @@ class BusSynchronizer(Module):
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sync_i += starter.eq(0)
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sync_i += starter.eq(0)
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self.submodules._ping = PulseSynchronizer(idomain, odomain)
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self.submodules._ping = PulseSynchronizer(idomain, odomain)
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self.submodules._pong = PulseSynchronizer(odomain, idomain)
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self.submodules._pong = PulseSynchronizer(odomain, idomain)
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self.submodules._timeout = WaitTimer(timeout)
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self.comb += [
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self.comb += [
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self._ping.i.eq(starter | self._pong.o),
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self._timeout.wait.eq(~self._ping.i),
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self._ping.i.eq(starter | self._pong.o | self._timeout.done),
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self._pong.i.eq(self._ping.i)
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self._pong.i.eq(self._ping.i)
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]
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]
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