build/xilinx/vivado: use GenericToolchain
This commit is contained in:
Gwenhael Goavec-Merou
parent
8446c5b342
commit
564c062074
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@ -15,6 +15,7 @@ from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import *
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from litex.build import tools
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from litex.build.xilinx import common
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from litex.build.generic_toolchain import GenericToolchain
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# Constraints (.xdc) -------------------------------------------------------------------------------
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@ -67,39 +68,6 @@ def _build_xdc(named_sc, named_pc):
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r += "\n" + "\n\n".join(named_pc)
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return r
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# Script -------------------------------------------------------------------------------------------
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def _build_script(build_name):
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if sys.platform in ["win32", "cygwin"]:
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script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n"
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script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
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script_file = "build_" + build_name + ".bat"
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tools.write_to_file(script_file, script_contents)
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else:
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script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
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if os.getenv("LITEX_ENV_VIVADO", False):
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script_contents += "source " + os.path.join(os.getenv("LITEX_ENV_VIVADO"), "settings64.sh\n")
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script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
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script_file = "build_" + build_name + ".sh"
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tools.write_to_file(script_file, script_contents)
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return script_file
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def _run_script(script):
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if sys.platform in ["win32", "cygwin"]:
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shell = ["cmd", "/c"]
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else:
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shell = ["bash"]
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if which("vivado") is None and os.getenv("LITEX_ENV_VIVADO", False) == False:
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msg = "Unable to find or source Vivado toolchain, please either:\n"
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msg += "- Source Vivado's settings manually.\n"
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msg += "- Or set LITEX_ENV_VIVADO environment variant to Vivado's settings path.\n"
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msg += "- Or add Vivado toolchain to your $PATH."
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raise OSError(msg)
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if tools.subprocess_call_filtered(shell + [script], common.colors) != 0:
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raise OSError("Error occured during Vivado's script execution.")
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# XilinxVivadoToolchain ----------------------------------------------------------------------------
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class XilinxVivadoCommands(list):
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@ -118,7 +86,7 @@ class XilinxVivadoCommands(list):
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return named_commands
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class XilinxVivadoToolchain:
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class XilinxVivadoToolchain(GenericToolchain):
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attr_translate = {
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"keep": ("dont_touch", "true"),
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"no_retiming": ("dont_touch", "true"),
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@ -130,6 +98,7 @@ class XilinxVivadoToolchain:
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}
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def __init__(self):
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super().__init__()
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self.bitstream_commands = []
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self.additional_commands = []
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self.pre_synthesis_commands = XilinxVivadoCommands()
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@ -142,28 +111,116 @@ class XilinxVivadoToolchain:
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self.vivado_post_place_phys_opt_directive = None
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self.vivado_route_directive = "default"
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self.vivado_post_route_phys_opt_directive = "default"
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self.clocks = dict()
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self.false_paths = set()
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self._synth_mode = "vivado"
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self._enable_xpm = False
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def _build_tcl(self, platform, build_name, synth_mode, enable_xpm, vns):
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assert synth_mode in ["vivado", "yosys"]
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def finalize(self):
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# Convert clocks and false path to platform commands
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self._build_clock_constraints()
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self._build_false_path_constraints()
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def build(self, platform, fragment,
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synth_mode = "vivado",
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enable_xpm = False,
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**kwargs):
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self._synth_mode = synth_mode
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self._enable_xpm = enable_xpm
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return self._build(platform, fragment, **kwargs)
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# Constraints (.xdc) ---------------------------------------------------------------------------
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def _format_xdc_constraint(self, c):
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if isinstance(c, Pins):
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return "set_property LOC " + c.identifiers[0]
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elif isinstance(c, IOStandard):
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return "set_property IOSTANDARD " + c.name
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elif isinstance(c, Drive):
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return "set_property DRIVE " + str(c.strength)
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elif isinstance(c, Misc):
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return "set_property " + c.misc.replace("=", " ")
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elif isinstance(c, Inverted):
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return None
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else:
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raise ValueError("unknown constraint {}".format(c))
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def build_io_constraints(self):
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r = _build_xdc(self.named_sc, self.named_pc)
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tools.write_to_file(self._build_name + ".xdc", r)
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return (self._build_name + ".xdc", "XDC")
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# Timing Constraints (in xdc file) -------------------------------------------------------------
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def _build_clock_constraints(self):
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self.platform.add_platform_command(_xdc_separator("Clock constraints"))
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def get_clk_type(clk):
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return {
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False : "nets",
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True : "ports",
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}[hasattr(clk, "port")]
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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self.platform.add_platform_command(
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"create_clock -name {clk} -period " + str(period) +
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" [get_" + get_clk_type(clk) + " {clk}]", clk=clk)
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for _from, _to in sorted(self.false_paths, key=lambda x: (x[0].duid, x[1].duid)):
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self.platform.add_platform_command(
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"set_clock_groups "
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"-group [get_clocks -include_generated_clocks -of [get_" + get_clk_type(_from) + " {_from}]] "
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"-group [get_clocks -include_generated_clocks -of [get_" + get_clk_type(_to) + " {_to}]] "
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"-asynchronous",
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_from=_from, _to=_to)
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# Make sure add_*_constraint cannot be used again
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self.clocks.clear()
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self.false_paths.clear()
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def _build_false_path_constraints(self):
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self.platform.add_platform_command(_xdc_separator("False path constraints"))
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# The asynchronous input to a MultiReg is a false path
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self.platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_nets -hierarchical -filter {{mr_ff == TRUE}}]"
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)
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# The asychronous reset input to the AsyncResetSynchronizer is a false path
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self.platform.add_platform_command(
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"set_false_path -quiet "
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"-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
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"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
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)
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# clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs
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self.platform.add_platform_command(
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"set_max_delay 2 -quiet "
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"-from [get_pins -filter {{REF_PIN_NAME == C}} "
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"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of_objects [get_cells -hierarchical -filter {{ars_ff2 == TRUE}}]]"
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)
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def build_timing_constraints(self, vns):
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# FIXME: -> self ?
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self._vns = vns
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# Project (.tcl) -------------------------------------------------------------------------------
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def build_project(self):
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assert self._synth_mode in ["vivado", "yosys"]
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tcl = []
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# Create project
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tcl.append("\n# Create Project\n")
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tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device))
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tcl.append("create_project -force -name {} -part {}".format(self._build_name, self.platform.device))
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tcl.append("set_msg_config -id {Common 17-55} -new_severity {Warning}")
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# Enable Xilinx Parameterized Macros
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if enable_xpm:
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if self._enable_xpm:
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tcl.append("\n# Enable Xilinx Parameterized Macros\n")
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tcl.append("set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]")
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# Add sources (when Vivado used for synthesis)
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if synth_mode == "vivado":
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if self._synth_mode == "vivado":
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tcl.append("\n# Add Sources\n")
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# "-include_dirs {}" crashes Vivado 2016.4
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for filename, language, library, *copy in platform.sources:
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for filename, language, library, *copy in self.platform.sources:
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filename_tcl = "{" + filename + "}"
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if (language == "systemverilog"):
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tcl.append("read_verilog -v " + filename_tcl)
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@ -180,13 +237,13 @@ class XilinxVivadoToolchain:
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# Add EDIFs
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tcl.append("\n# Add EDIFs\n")
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for filename in platform.edifs:
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for filename in self.platform.edifs:
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filename_tcl = "{" + filename + "}"
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tcl.append("read_edif " + filename_tcl)
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# Add IPs
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tcl.append("\n# Add IPs\n")
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for filename, disable_constraints in platform.ips.items():
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for filename, disable_constraints in self.platform.ips.items():
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if filename.endswith("tcl"):
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tcl += open(filename, "r").read().splitlines()
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else:
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@ -202,31 +259,31 @@ class XilinxVivadoToolchain:
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# Add constraints
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tcl.append("\n# Add constraints\n")
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tcl.append("read_xdc {}.xdc".format(build_name))
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tcl.append("set_property PROCESSING_ORDER EARLY [get_files {}.xdc]".format(build_name))
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tcl.append("read_xdc {}.xdc".format(self._build_name))
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tcl.append("set_property PROCESSING_ORDER EARLY [get_files {}.xdc]".format(self._build_name))
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# Add pre-synthesis commands
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tcl.append("\n# Add pre-synthesis commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands.resolve(vns))
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tcl.extend(c.format(build_name=self._build_name) for c in self.pre_synthesis_commands.resolve(self._vns))
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# Synthesis
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if synth_mode == "vivado":
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if self._synth_mode == "vivado":
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tcl.append("\n# Synthesis\n")
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synth_cmd = "synth_design -directive {} -top {} -part {}".format(self.vivado_synth_directive,
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build_name, platform.device)
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if platform.verilog_include_paths:
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synth_cmd += " -include_dirs {{{}}}".format(" ".join(platform.verilog_include_paths))
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self._build_name, self.platform.device)
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if self.platform.verilog_include_paths:
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synth_cmd += " -include_dirs {{{}}}".format(" ".join(self.platform.verilog_include_paths))
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tcl.append(synth_cmd)
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elif synth_mode == "yosys":
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elif self._synth_mode == "yosys":
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tcl.append("\n# Read Yosys EDIF\n")
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tcl.append("read_edif {}.edif".format(build_name))
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tcl.append("link_design -top {} -part {}".format(build_name, platform.device))
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tcl.append("read_edif {}.edif".format(self._build_name))
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tcl.append("link_design -top {} -part {}".format(self._build_name, self.platform.device))
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else:
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raise OSError("Unknown synthesis mode! {}".format(synth_mode))
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raise OSError("Unknown synthesis mode! {}".format(self._synth_mode))
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tcl.append("\n# Synthesis report\n")
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tcl.append("report_timing_summary -file {}_timing_synth.rpt".format(build_name))
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
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tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
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tcl.append("report_timing_summary -file {}_timing_synth.rpt".format(self._build_name))
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(self._build_name))
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tcl.append("report_utilization -file {}_utilization_synth.rpt".format(self._build_name))
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# Optimize
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tcl.append("\n# Optimize design\n")
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@ -235,11 +292,11 @@ class XilinxVivadoToolchain:
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# Incremental implementation
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if self.incremental_implementation:
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tcl.append("\n# Read design checkpoint\n")
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tcl.append("read_checkpoint -incremental {}_route.dcp".format(build_name))
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tcl.append("read_checkpoint -incremental {}_route.dcp".format(self._build_name))
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# Add pre-placement commands
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tcl.append("\n# Add pre-placement commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_placement_commands.resolve(vns))
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tcl.extend(c.format(build_name=self._build_name) for c in self.pre_placement_commands.resolve(self._vns))
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# Placement
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tcl.append("\n# Placement\n")
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@ -247,154 +304,77 @@ class XilinxVivadoToolchain:
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if self.vivado_post_place_phys_opt_directive:
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tcl.append("phys_opt_design -directive {}".format(self.vivado_post_place_phys_opt_directive))
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tcl.append("\n# Placement report\n")
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
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tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
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tcl.append("report_io -file {}_io.rpt".format(build_name))
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tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
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tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(self._build_name))
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tcl.append("report_utilization -file {}_utilization_place.rpt".format(self._build_name))
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tcl.append("report_io -file {}_io.rpt".format(self._build_name))
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tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(self._build_name))
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tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(self._build_name))
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# Add pre-routing commands
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tcl.append("\n# Add pre-routing commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_routing_commands.resolve(vns))
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tcl.extend(c.format(build_name=self._build_name) for c in self.pre_routing_commands.resolve(self._vns))
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# Routing
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tcl.append("\n# Routing\n")
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tcl.append("route_design -directive {}".format(self.vivado_route_directive))
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tcl.append("phys_opt_design -directive {}".format(self.vivado_post_route_phys_opt_directive))
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tcl.append("write_checkpoint -force {}_route.dcp".format(build_name))
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tcl.append("write_checkpoint -force {}_route.dcp".format(self._build_name))
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tcl.append("\n# Routing report\n")
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tcl.append("report_timing_summary -no_header -no_detailed_paths")
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tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
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tcl.append("report_drc -file {}_drc.rpt".format(build_name))
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tcl.append("report_timing_summary -datasheet -max_paths 10 -file {}_timing.rpt".format(build_name))
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tcl.append("report_power -file {}_power.rpt".format(build_name))
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tcl.append("report_route_status -file {}_route_status.rpt".format(self._build_name))
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tcl.append("report_drc -file {}_drc.rpt".format(self._build_name))
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tcl.append("report_timing_summary -datasheet -max_paths 10 -file {}_timing.rpt".format(self._build_name))
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tcl.append("report_power -file {}_power.rpt".format(self._build_name))
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for bitstream_command in self.bitstream_commands:
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tcl.append(bitstream_command.format(build_name=build_name))
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tcl.append(bitstream_command.format(build_name=self._build_name))
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# Bitstream generation
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tcl.append("\n# Bitstream generation\n")
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tcl.append("write_bitstream -force {}.bit ".format(build_name))
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tcl.append("write_bitstream -force {}.bit ".format(self._build_name))
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for additional_command in self.additional_commands:
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tcl.append(additional_command.format(build_name=build_name))
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tcl.append(additional_command.format(build_name=self._build_name))
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# Quit
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tcl.append("\n# End\n")
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tcl.append("quit")
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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tools.write_to_file(self._build_name + ".tcl", "\n".join(tcl))
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def _build_clock_constraints(self, platform):
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platform.add_platform_command(_xdc_separator("Clock constraints"))
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def get_clk_type(clk):
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return {
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False : "nets",
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True : "ports",
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}[hasattr(clk, "port")]
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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platform.add_platform_command(
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"create_clock -name {clk} -period " + str(period) +
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" [get_" + get_clk_type(clk) + " {clk}]", clk=clk)
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for _from, _to in sorted(self.false_paths, key=lambda x: (x[0].duid, x[1].duid)):
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platform.add_platform_command(
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"set_clock_groups "
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"-group [get_clocks -include_generated_clocks -of [get_" + get_clk_type(_from) + " {_from}]] "
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"-group [get_clocks -include_generated_clocks -of [get_" + get_clk_type(_to) + " {_to}]] "
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"-asynchronous",
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_from=_from, _to=_to)
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# Make sure add_*_constraint cannot be used again
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del self.clocks
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del self.false_paths
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# Script ---------------------------------------------------------------------------------------
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def _build_false_path_constraints(self, platform):
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platform.add_platform_command(_xdc_separator("False path constraints"))
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# The asynchronous input to a MultiReg is a false path
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_nets -hierarchical -filter {{mr_ff == TRUE}}]"
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)
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# The asychronous reset input to the AsyncResetSynchronizer is a false path
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platform.add_platform_command(
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"set_false_path -quiet "
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"-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
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"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
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)
|
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# clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs
|
||||
platform.add_platform_command(
|
||||
"set_max_delay 2 -quiet "
|
||||
"-from [get_pins -filter {{REF_PIN_NAME == C}} "
|
||||
"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE}}]] "
|
||||
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
|
||||
"-of_objects [get_cells -hierarchical -filter {{ars_ff2 == TRUE}}]]"
|
||||
)
|
||||
def build_script(self):
|
||||
if sys.platform in ["win32", "cygwin"]:
|
||||
script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n"
|
||||
script_contents += "vivado -mode batch -source " + self._build_name + ".tcl\n"
|
||||
script_file = "build_" + self._build_name + ".bat"
|
||||
tools.write_to_file(script_file, script_contents)
|
||||
else:
|
||||
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
|
||||
if os.getenv("LITEX_ENV_VIVADO", False):
|
||||
script_contents += "source " + os.path.join(os.getenv("LITEX_ENV_VIVADO"), "settings64.sh\n")
|
||||
script_contents += "vivado -mode batch -source " + self._build_name + ".tcl\n"
|
||||
script_file = "build_" + self._build_name + ".sh"
|
||||
tools.write_to_file(script_file, script_contents)
|
||||
return script_file
|
||||
|
||||
def run_script(self, script):
|
||||
if synth_mode == "yosys":
|
||||
common._run_yosys(self.platform.device, self.platform.sources,
|
||||
self.platform.verilog_include_paths, self._build_name)
|
||||
if sys.platform in ["win32", "cygwin"]:
|
||||
shell = ["cmd", "/c"]
|
||||
else:
|
||||
shell = ["bash"]
|
||||
|
||||
def build(self, platform, fragment,
|
||||
build_dir = "build",
|
||||
build_name = "top",
|
||||
run = True,
|
||||
synth_mode = "vivado",
|
||||
enable_xpm = False,
|
||||
**kwargs):
|
||||
if which("vivado") is None and os.getenv("LITEX_ENV_VIVADO", False) == False:
|
||||
msg = "Unable to find or source Vivado toolchain, please either:\n"
|
||||
msg += "- Source Vivado's settings manually.\n"
|
||||
msg += "- Or set LITEX_ENV_VIVADO environment variant to Vivado's settings path.\n"
|
||||
msg += "- Or add Vivado toolchain to your $PATH."
|
||||
raise OSError(msg)
|
||||
|
||||
# Create build directory
|
||||
os.makedirs(build_dir, exist_ok=True)
|
||||
cwd = os.getcwd()
|
||||
os.chdir(build_dir)
|
||||
if tools.subprocess_call_filtered(shell + [script], common.colors) != 0:
|
||||
raise OSError("Error occured during Vivado's script execution.")
|
||||
|
||||
# Finalize design
|
||||
if not isinstance(fragment, _Fragment):
|
||||
fragment = fragment.get_fragment()
|
||||
platform.finalize(fragment)
|
||||
|
||||
# Generate verilog
|
||||
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
|
||||
|
||||
# Generate timing constraints
|
||||
self._build_clock_constraints(platform)
|
||||
self._build_false_path_constraints(platform)
|
||||
|
||||
# Add verilog to project.
|
||||
named_sc, named_pc = platform.resolve_signals(v_output.ns)
|
||||
v_file = build_name + ".v"
|
||||
v_output.write(v_file)
|
||||
platform.add_source(v_file)
|
||||
|
||||
# Generate design project (.tcl)
|
||||
self._build_tcl(
|
||||
platform = platform,
|
||||
build_name = build_name,
|
||||
synth_mode = synth_mode,
|
||||
enable_xpm = enable_xpm,
|
||||
vns = v_output.ns,
|
||||
)
|
||||
|
||||
# Generate design constraints (.xdc)
|
||||
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
|
||||
|
||||
# Run
|
||||
if run:
|
||||
if synth_mode == "yosys":
|
||||
common._run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
|
||||
script = _build_script(build_name)
|
||||
_run_script(script)
|
||||
|
||||
os.chdir(cwd)
|
||||
|
||||
return v_output.ns
|
||||
|
||||
def add_period_constraint(self, platform, clk, period):
|
||||
clk.attr.add("keep")
|
||||
period = math.floor(period*1e3)/1e3 # round to lowest picosecond
|
||||
if clk in self.clocks:
|
||||
if period != self.clocks[clk]:
|
||||
raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
|
||||
.format(self.clocks[clk], period))
|
||||
self.clocks[clk] = period
|
||||
|
||||
def add_false_path_constraint(self, platform, from_, to):
|
||||
from_.attr.add("keep")
|
||||
to.attr.add("keep")
|
||||
if (to, from_) not in self.false_paths:
|
||||
self.false_paths.add((from_, to))
|
||||
|
||||
def vivado_build_args(parser):
|
||||
toolchain_group = parser.add_argument_group(title="Toolchain options")
|
||||
|
|
|
|||
Loading…
Reference in New Issue