Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

cores/uart: minor cleanups on RS232PHYRX/TX.

Browse source
This commit is contained in:
Florent Kermarrec 2020-08-28 09:28:12 +02:00
parent 587e09e3d6
commit 566fbd60c3
1 changed files with 22 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
litex/soc/cores/uart.py
View file

@ -40,8 +40,8 @@ class RS232PHYRX(Module):
# # # # # #
uart_clk_rxen = Signal() rx_clken = Signal()
phase_accumulator_rx = Signal(32, reset_less=True) rx_clkphase = Signal(32, reset_less=True)
rx = Signal() rx = Signal()
rx_r = Signal() rx_r = Signal()
@ -60,7 +60,7 @@ class RS232PHYRX(Module):
rx_bitcount.eq(0), rx_bitcount.eq(0),
) )
).Else( ).Else(
If(uart_clk_rxen, If(rx_clken,
rx_bitcount.eq(rx_bitcount + 1), rx_bitcount.eq(rx_bitcount + 1),
If(rx_bitcount == 0, If(rx_bitcount == 0,
If(rx, # verify start bit If(rx, # verify start bit
@ -78,12 +78,13 @@ class RS232PHYRX(Module):
) )
) )
] ]
self.sync += \ self.sync += [
If(rx_busy, If(rx_busy,
Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + tuning_word) Cat(rx_clkphase, rx_clken).eq(rx_clkphase + tuning_word)
).Else( ).Else(
Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31) Cat(rx_clkphase, rx_clken).eq(2**31)
) )
]
class RS232PHYTX(Module): class RS232PHYTX(Module):
@ -92,8 +93,8 @@ class RS232PHYTX(Module):
# # # # # #
uart_clk_txen = Signal() tx_clken = Signal()
phase_accumulator_tx = Signal(32, reset_less=True) tx_clkphase = Signal(32, reset_less=True)
pads.tx.reset = 1 pads.tx.reset = 1
@ -107,7 +108,7 @@ class RS232PHYTX(Module):
tx_bitcount.eq(0), tx_bitcount.eq(0),
tx_busy.eq(1), tx_busy.eq(1),
pads.tx.eq(0) pads.tx.eq(0)
).Elif(uart_clk_txen & tx_busy, ).Elif(tx_clken & tx_busy,
tx_bitcount.eq(tx_bitcount + 1), tx_bitcount.eq(tx_bitcount + 1),
If(tx_bitcount == 8, If(tx_bitcount == 8,
pads.tx.eq(1) pads.tx.eq(1)
@ -123,9 +124,9 @@ class RS232PHYTX(Module):
] ]
self.sync += [ self.sync += [
If(tx_busy, If(tx_busy,
Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word) Cat(tx_clkphase, tx_clken).eq(tx_clkphase + tuning_word)
).Else( ).Else(
Cat(phase_accumulator_tx, uart_clk_txen).eq(tuning_word) Cat(tx_clkphase, tx_clken).eq(tuning_word)
) )
] ]