Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

wishbone: add missing SEL

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2011-12-08 19:09:32 +01:00
parent ed05ec5f6a
commit 5720a51dad
1 changed files with 1 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
migen/bus/wishbone.py
View file

@ -5,6 +5,7 @@ _desc = [
(True, "adr", 32),
(True, "dat", 32),
(False, "dat", 32),
(True, "sel", 4),
(True, "cyc", 1),
(True, "stb", 1),
(False, "ack", 1),