Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

pytholite/compiler: improve naming of selection signals

This commit is contained in:
Sebastien Bourdeauducq 2012-11-09 20:19:22 +01:00
parent 4921a34616
commit 5750c7c07e
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
migen/pytholite/compiler.py
View File

@ -29,7 +29,8 @@ class _LowerAbstractLoad(fhdl.NodeTransformer):
class _Register:
def __init__(self, name, nbits):
self.storage = Signal(BV(nbits), name=name)
self.name = name
self.storage = Signal(BV(nbits), name=self.name)
self.source_encoding = {}
self.finalized = False
@ -41,7 +42,7 @@ class _Register:
def finalize(self):
if self.finalized:
raise FinalizeError
self.sel = Signal(BV(bits_for(len(self.source_encoding) + 1)), name="pl_regsel")
self.sel = Signal(BV(bits_for(len(self.source_encoding) + 1)), name="pl_regsel_"+self.name)
self.finalized = True
def get_fragment(self):