litespi/integration: Review/Cleanup #1024.
Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker); simplify things for now: - Avoid duplication in spiflash_freq_init. - Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h). - Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
This commit is contained in:
Florent Kermarrec
parent
aff2aefa72
commit
575af6fc60
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@ -1491,7 +1491,7 @@ class LiteXSoC(SoC):
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self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
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# Add SPI Flash --------------------------------------------------------------------------------
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def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, init=None, clock_domain="sys", **kwargs):
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def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, phy=None, **kwargs):
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if module is None:
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# Use previous LiteX SPI Flash core with compat, will be deprecated at some point.
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from litex.compat.soc_add_spi_flash import add_spi_flash
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@ -1500,34 +1500,30 @@ class LiteXSoC(SoC):
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else:
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# Imports.
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from litespi import LiteSPI
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from litespi.phy.generic import LiteSPIPHY
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from litespi.opcodes import SpiNorFlashOpCodes
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# Checks/Parameters.
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assert mode in ["1x", "4x"]
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if clk_freq is None: clk_freq = self.sys_clk_freq
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# Core.
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# PHY.
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spiflash_phy = phy
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if spiflash_phy is None:
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self.check_if_exists(name + "_phy")
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self.check_if_exists(name + "_mmap")
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spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
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if init is None:
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from litespi.phy.generic import LiteSPIPHY
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if not hasattr(spiflash_pads, "clk") or self.platform.device.startswith("LFE5U") or self.platform.device.startswith("LAE5U"):
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spiflash_phy = LiteSPIPHY(spiflash_pads, module, clock_domain=clock_domain, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), legacy=True)
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self.add_constant("SPIFLASH_LEGACY")
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else:
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spiflash_phy = LiteSPIPHY(spiflash_pads, module, clock_domain=clock_domain, device=self.platform.device, legacy=False)
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else:
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from litespi.phy.model import LiteSPIPHYModel
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spiflash_phy = LiteSPIPHYModel(module, init=init, clock_domain=clock_domain)
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spiflash_core = LiteSPI(spiflash_phy, clock_domain=clock_domain, mmap_endianness=self.cpu.endianness, **kwargs)
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spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq))
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setattr(self.submodules, name + "_phy", spiflash_phy)
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# Core.
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self.check_if_exists(name + "_mmap")
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spiflash_core = LiteSPI(spiflash_phy, mmap_endianness=self.cpu.endianness, **kwargs)
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setattr(self.submodules, name + "_core", spiflash_core)
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spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
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self.bus.add_slave(name=name, slave=spiflash_core.bus, region=spiflash_region)
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# Constants.
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self.add_constant("SPIFLASH_FREQUENCY", clk_freq)
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self.add_constant("SPIFLASH_PHY_FREQUENCY", clk_freq)
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self.add_constant("SPIFLASH_MODULE_NAME", module.name.upper())
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self.add_constant("SPIFLASH_MODULE_TOTAL_SIZE", module.total_size)
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self.add_constant("SPIFLASH_MODULE_PAGE_SIZE", module.page_size)
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@ -13,47 +13,20 @@
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#include "spiflash.h"
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//#define SPIFLASH_DEBUG
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#if defined(CSR_SPIFLASH_CORE_BASE)
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#if defined(SPIFLASH_LEGACY)
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int spiflash_freq_init(void)
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{
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unsigned int lowest_div = spiflash_phy_clk_divisor_read();
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unsigned int crc = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
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unsigned int crc_test = crc;
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#if SPIFLASH_DEBUG
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printf("Testing against CRC32: %08x\n\r", crc);
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#endif
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#ifdef CSR_SPIFLASH_PHY_CLK_DIVISOR_ADDR
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/* Check if block is erased (filled with 0xFF) */
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if(crc == CRC32_ERASED_FLASH) {
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printf("Block of size %d, started on address 0x%lx is erased. Cannot proceed with SPI Flash frequency test.\n\r", SPI_FLASH_BLOCK_SIZE, SPIFLASH_BASE);
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return -1;
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}
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unsigned int lowest_div, crc, crc_test;
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while((crc == crc_test) && (lowest_div-- > 0)) {
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spiflash_phy_clk_divisor_write((uint32_t)lowest_div);
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crc_test = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
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#if SPIFLASH_DEBUG
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printf("[DIV: %d] %08x\n\r", lowest_div, crc_test);
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#endif
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}
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lowest_div++;
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printf("SPI Flash clk configured to %d MHz\n", (spiflash_frequency_read()/(2*(1 + lowest_div)))/1000000);
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spiflash_phy_clk_divisor_write(lowest_div);
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return 0;
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}
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#else
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int spiflash_freq_init(void)
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{
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unsigned int crc = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
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unsigned int crc_test = crc;
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lowest_div = spiflash_phy_clk_divisor_read();
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crc = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
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crc_test = crc;
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#if SPIFLASH_DEBUG
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printf("Testing against CRC32: %08x\n\r", crc);
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@ -65,12 +38,27 @@ int spiflash_freq_init(void)
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return -1;
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}
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printf("SPI Flash clk configured to %ld MHz\n", (unsigned long)(spiflash_frequency_read()/1e6));
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while((crc == crc_test) && (lowest_div-- > 0)) {
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spiflash_phy_clk_divisor_write((uint32_t)lowest_div);
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crc_test = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
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#if SPIFLASH_DEBUG
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printf("[DIV: %d] %08x\n\r", lowest_div, crc_test);
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#endif
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}
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lowest_div++;
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printf("SPI Flash clk configured to %d MHz\n", (SPIFLASH_PHY_FREQUENCY/(2*(1 + lowest_div)))/1000000);
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spiflash_phy_clk_divisor_write(lowest_div);
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#else
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printf("SPI Flash clk configured to %ld MHz\n", (unsigned long)(SPIFLASH_PHY_FREQUENCY/1e6));
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#endif
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return 0;
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}
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#endif // SPIFLASH_LEGACY
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void spiflash_dummy_bits_setup(unsigned int dummy_bits)
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{
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spiflash_core_mmap_dummy_bits_write((uint32_t)dummy_bits);
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@ -116,7 +116,7 @@ class SimSoC(SoCCore):
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with_i2c = False,
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with_sdcard = False,
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with_spi_flash = False,
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flash_init = [],
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spi_flash_init = [],
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sim_debug = False,
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trace_reset_on = False,
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**kwargs):
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@ -252,12 +252,15 @@ class SimSoC(SoCCore):
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.phy.model import LiteSPIPHYModel
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from litespi.modules import S25FL128L
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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if flash_init is None:
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spiflash_module = S25FL128L(Codes.READ_1_1_4)
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if spi_flash_init is None:
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platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/iddr_verilog.v")
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platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/oddr_verilog.v")
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self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True, init=flash_init)
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self.submodules.spiflash_phy = LiteSPIPHYModel(spiflash_module, init=spi_flash_init)
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self.add_spi_flash(phy=self.spiflash_phy, mode="4x", module=spiflash_module, with_master=True)
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# Simulation debugging ----------------------------------------------------------------------
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if sim_debug:
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@ -323,7 +326,7 @@ def sim_args(parser):
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parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
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parser.add_argument("--flash-init", default=None, help="Flash init file")
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parser.add_argument("--spi_flash-init", default=None, help="SPI Flash init file")
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parser.add_argument("--trace", action="store_true", help="Enable Tracing")
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parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)")
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parser.add_argument("--trace-start", default="0", help="Time to start tracing (ps)")
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@ -394,7 +397,7 @@ def main():
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sim_debug = args.sim_debug,
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trace_reset_on = trace_start > 0 or trace_end > 0,
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sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
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flash_init = None if args.flash_init is None else get_mem_data(args.flash_init, "big"),
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spi_flash_init = None if args.spi_flash_init is None else get_mem_data(args.spi_flash_init, "big"),
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**soc_kwargs)
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if args.ram_init is not None or args.sdram_init is not None:
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soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
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