build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route
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@ -113,24 +113,16 @@ def _build_tcl(platform, sources, build_dir, build_name):
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# import timing constraints
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tcl.append("import_files -convert_EDN_to_HDL 0 -sdc {{{}}}".format(build_name + ".sdc"))
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for tool in ["{SYNTHESIZE}", "{PLACEROUTE}", "{VERIFYTIMING}"]:
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tcl.append(" ".join(["organize_tool_files",
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"-tool " + tool,
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"-file impl/constraint/{}.sdc".format(build_name),
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"-module {}".format(build_name),
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"-input_type {constraint}"
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]))
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tcl.append(" ".join(["organize_tool_files",
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"-tool {VERIFYTIMING}",
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"-file impl/constraint/{}.sdc".format(build_name),
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"-module {}".format(build_name),
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"-input_type {constraint}"
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]))
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# build flow
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tcl.append("run_tool -name {CONSTRAINT_MANAGEMENT}")
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tcl.append("run_tool -name {SYNTHESIZE}")
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tcl.append(" ".join([
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"configure_tool",
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"-name {PLACEROUTE}",
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"-params {EFFORT_LEVEL:true}",
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"-params {REPAIR_MIN_DELAY:true}",
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"-params {TDPR:true}"
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]))
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tcl.append("run_tool -name {PLACEROUTE}")
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tcl.append("run_tool -name {GENERATEPROGRAMMINGDATA}")
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tcl.append("run_tool -name {GENERATEPROGRAMMINGFILE}")
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