build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route

This commit is contained in:
Florent Kermarrec 2018-11-19 15:54:33 +01:00
parent 85f7666207
commit 5805d63013
1 changed files with 6 additions and 14 deletions

View File

@ -113,9 +113,8 @@ def _build_tcl(platform, sources, build_dir, build_name):
# import timing constraints
tcl.append("import_files -convert_EDN_to_HDL 0 -sdc {{{}}}".format(build_name + ".sdc"))
for tool in ["{SYNTHESIZE}", "{PLACEROUTE}", "{VERIFYTIMING}"]:
tcl.append(" ".join(["organize_tool_files",
"-tool " + tool,
"-tool {VERIFYTIMING}",
"-file impl/constraint/{}.sdc".format(build_name),
"-module {}".format(build_name),
"-input_type {constraint}"
@ -124,13 +123,6 @@ def _build_tcl(platform, sources, build_dir, build_name):
# build flow
tcl.append("run_tool -name {CONSTRAINT_MANAGEMENT}")
tcl.append("run_tool -name {SYNTHESIZE}")
tcl.append(" ".join([
"configure_tool",
"-name {PLACEROUTE}",
"-params {EFFORT_LEVEL:true}",
"-params {REPAIR_MIN_DELAY:true}",
"-params {TDPR:true}"
]))
tcl.append("run_tool -name {PLACEROUTE}")
tcl.append("run_tool -name {GENERATEPROGRAMMINGDATA}")
tcl.append("run_tool -name {GENERATEPROGRAMMINGFILE}")