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picorv32: add reset signal

This commit is contained in:
Florent Kermarrec 2018-08-07 08:59:34 +02:00
parent 0429ee9f8f
commit 580efecc8c
1 changed files with 2 additions and 1 deletions
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3
litex/soc/cores/cpu/picorv32/core.py
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@ -7,6 +7,7 @@ from litex.soc.interconnect import wishbone
class PicoRV32(Module): class PicoRV32(Module):
def __init__(self, platform, progaddr_reset, variant): def __init__(self, platform, progaddr_reset, variant):
self.reset = Signal()
self.ibus = i = wishbone.Interface() self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface() self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32) self.interrupt = Signal(32)
@ -50,7 +51,7 @@ class PicoRV32(Module):
# clock / reset # clock / reset
i_clk=ClockSignal(), i_clk=ClockSignal(),
i_resetn=~ResetSignal(), i_resetn=~(ResetSignal() | self.reset),
# trap # trap
o_trap=self.trap, o_trap=self.trap,