lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
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@ -42,20 +42,13 @@ class Reader(Module):
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request_enable.eq(rsv_level != fifo_depth)
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]
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# data available
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data_available = lasmim.dat_ack
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for i in range(lasmim.read_latency):
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new_data_available = Signal()
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self.sync += new_data_available.eq(data_available)
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data_available = new_data_available
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# FIFO
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fifo = SyncFIFO(lasmim.dw, fifo_depth)
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self.submodules += fifo
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self.comb += [
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fifo.din.eq(lasmim.dat_r),
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fifo.we.eq(data_available),
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fifo.we.eq(lasmim.dat_r_ack),
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self.data.stb.eq(fifo.readable),
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fifo.re.eq(self.data.ack),
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@ -86,14 +79,8 @@ class Writer(Module):
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fifo.din.eq(self.address_data.d)
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]
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data_valid = lasmim.dat_ack
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for i in range(lasmim.write_latency):
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new_data_valid = Signal()
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self.sync += new_data_valid.eq(data_valid),
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data_valid = new_data_valid
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self.comb += [
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fifo.re.eq(data_valid),
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fifo.re.eq(lasmim.dat_w_ack),
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If(data_valid,
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lasmim.dat_we.eq(2**(lasmim.dw//8)-1),
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lasmim.dat_w.eq(fifo.dout)
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