framebuffer: indentation
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@ -187,19 +187,20 @@ class FIFO(Actor):
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],
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clkport="clk_write")
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t = self.token("dac")
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return Fragment([
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asfifo.ins["read_en"].eq(1),
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return Fragment(
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[
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asfifo.ins["read_en"].eq(1),
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self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
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asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
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asfifo.ins["data_in"].eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
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self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
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asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
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asfifo.ins["data_in"].eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
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self.busy.eq(0),
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asfifo.ins["rst"].eq(0)
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], [
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Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
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],
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instances=[asfifo])
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self.busy.eq(0),
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asfifo.ins["rst"].eq(0)
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], [
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Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
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],
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instances=[asfifo])
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class FakeDMA(Actor):
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def __init__(self, port):
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