soc/interconnect/stream: add separators, mode Actor modules just after Endpoint
This commit is contained in:
Florent Kermarrec
parent
59995c5359
commit
59bf04d965
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@ -4,14 +4,18 @@
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# License: BSD
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import math
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from copy import copy
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from migen import *
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from migen.util.misc import xdir
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from migen.genlib.record import *
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from migen.genlib import fifo
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from litex.soc.interconnect.csr import *
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# Endpoint -----------------------------------------------------------------------------------------
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(DIR_SINK, DIR_SOURCE) = range(2)
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def _make_m2s(layout):
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@ -64,6 +68,91 @@ class Endpoint(Record):
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except:
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return getattr(object.__getattribute__(self, "param"), name)
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# Actor --------------------------------------------------------------------------------------------
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def _rawbits_layout(l):
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if isinstance(l, int):
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return [("rawbits", l)]
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else:
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return l
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def pack_layout(l, n):
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return [("chunk"+str(i), l) for i in range(n)]
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def get_endpoints(obj, filt=Endpoint):
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if hasattr(obj, "get_endpoints") and callable(obj.get_endpoints):
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return obj.get_endpoints(filt)
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r = dict()
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for k, v in xdir(obj, True):
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if isinstance(v, filt):
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r[k] = v
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return r
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def get_single_ep(obj, filt):
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eps = get_endpoints(obj, filt)
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if len(eps) != 1:
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raise ValueError("More than one endpoint")
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return list(eps.items())[0]
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class BinaryActor(Module):
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def __init__(self, *args, **kwargs):
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self.build_binary_control(self.sink, self.source, *args, **kwargs)
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def build_binary_control(self, sink, source):
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raise NotImplementedError("Binary actor classes must overload build_binary_control_fragment")
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class CombinatorialActor(BinaryActor):
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def build_binary_control(self, sink, source):
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self.comb += [
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source.valid.eq(sink.valid),
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source.first.eq(sink.first),
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source.last.eq(sink.last),
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sink.ready.eq(source.ready),
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]
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class PipelinedActor(BinaryActor):
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def __init__(self, latency):
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self.latency = latency
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self.pipe_ce = Signal()
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self.busy = Signal()
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BinaryActor.__init__(self, latency)
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def build_binary_control(self, sink, source, latency):
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busy = 0
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valid = sink.valid
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for i in range(latency):
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valid_n = Signal()
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self.sync += If(self.pipe_ce, valid_n.eq(valid))
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valid = valid_n
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busy = busy | valid
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self.comb += [
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self.pipe_ce.eq(source.ready | ~valid),
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sink.ready.eq(self.pipe_ce),
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source.valid.eq(valid),
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self.busy.eq(busy)
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]
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first = sink.valid & sink.first
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last = sink.valid & sink.last
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for i in range(latency):
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first_n = Signal()
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last_n = Signal()
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self.sync += \
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If(self.pipe_ce,
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first_n.eq(first),
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last_n.eq(last)
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)
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first = first_n
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last = last_n
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self.comb += [
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source.first.eq(first),
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source.last.eq(last)
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]
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# FIFO ---------------------------------------------------------------------------------------------
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class _FIFOWrapper(Module):
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def __init__(self, fifo_class, layout, depth):
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@ -120,6 +209,7 @@ class AsyncFIFO(_FIFOWrapper):
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fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
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layout, depth)
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# Mux/Demux ----------------------------------------------------------------------------------------
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class Multiplexer(Module):
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def __init__(self, layout, n):
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@ -156,6 +246,7 @@ class Demultiplexer(Module):
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cases[i] = self.sink.connect(source)
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self.comb += Case(self.sel, cases)
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# Converter ----------------------------------------------------------------------------------------
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class _UpConverter(Module):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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@ -367,6 +458,7 @@ class StrideConverter(Module):
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else:
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raise ValueError
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# Gearbox ------------------------------------------------------------------------------------------
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def lcm(a, b):
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return (a*b)//math.gcd(a, b)
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@ -433,6 +525,7 @@ class Gearbox(Module):
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else:
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self.comb += source.data.eq(o_data[::-1])
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# Monitor ------------------------------------------------------------------------------------------
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class Monitor(Module, AutoCSR):
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def __init__(self, endpoint, count_width=32, clock_domain="sys",
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@ -501,94 +594,7 @@ class Monitor(Module, AutoCSR):
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underflow_counter = MonitorCounter(reset, latch, ~endpoint.valid & endpoint.ready, self.underflows.status)
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self.submodules += underflow_counter
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# TODO: clean up code below
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# XXX
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from copy import copy
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from migen.util.misc import xdir
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def _rawbits_layout(l):
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if isinstance(l, int):
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return [("rawbits", l)]
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else:
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return l
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def pack_layout(l, n):
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return [("chunk"+str(i), l) for i in range(n)]
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def get_endpoints(obj, filt=Endpoint):
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if hasattr(obj, "get_endpoints") and callable(obj.get_endpoints):
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return obj.get_endpoints(filt)
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r = dict()
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for k, v in xdir(obj, True):
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if isinstance(v, filt):
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r[k] = v
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return r
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def get_single_ep(obj, filt):
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eps = get_endpoints(obj, filt)
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if len(eps) != 1:
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raise ValueError("More than one endpoint")
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return list(eps.items())[0]
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class BinaryActor(Module):
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def __init__(self, *args, **kwargs):
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self.build_binary_control(self.sink, self.source, *args, **kwargs)
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def build_binary_control(self, sink, source):
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raise NotImplementedError("Binary actor classes must overload build_binary_control_fragment")
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class CombinatorialActor(BinaryActor):
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def build_binary_control(self, sink, source):
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self.comb += [
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source.valid.eq(sink.valid),
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source.first.eq(sink.first),
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source.last.eq(sink.last),
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sink.ready.eq(source.ready),
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]
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class PipelinedActor(BinaryActor):
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def __init__(self, latency):
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self.latency = latency
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self.pipe_ce = Signal()
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self.busy = Signal()
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BinaryActor.__init__(self, latency)
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def build_binary_control(self, sink, source, latency):
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busy = 0
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valid = sink.valid
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for i in range(latency):
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valid_n = Signal()
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self.sync += If(self.pipe_ce, valid_n.eq(valid))
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valid = valid_n
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busy = busy | valid
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self.comb += [
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self.pipe_ce.eq(source.ready | ~valid),
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sink.ready.eq(self.pipe_ce),
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source.valid.eq(valid),
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self.busy.eq(busy)
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]
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first = sink.valid & sink.first
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last = sink.valid & sink.last
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for i in range(latency):
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first_n = Signal()
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last_n = Signal()
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self.sync += \
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If(self.pipe_ce,
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first_n.eq(first),
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last_n.eq(last)
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)
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first = first_n
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last = last_n
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self.comb += [
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source.first.eq(first),
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source.last.eq(last)
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]
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# Buffer -------------------------------------------------------------------------------------------
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class Buffer(PipelinedActor):
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def __init__(self, layout):
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@ -601,6 +607,7 @@ class Buffer(PipelinedActor):
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self.source.param.eq(self.sink.param)
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)
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# Cast ---------------------------------------------------------------------------------------------
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class Cast(CombinatorialActor):
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def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False):
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@ -620,6 +627,7 @@ class Cast(CombinatorialActor):
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raise TypeError
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self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
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# Unpack/Pack --------------------------------------------------------------------------------------
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class Unpack(Module):
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def __init__(self, n, layout_to, reverse=False):
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@ -715,6 +723,7 @@ class Pack(Module):
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)
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]
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# Pipeline -----------------------------------------------------------------------------------------
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class Pipeline(Module):
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def __init__(self, *modules):
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@ -742,6 +751,7 @@ class Pipeline(Module):
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if hasattr(m, "source"):
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self.source = m.source
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# BufferizeEndpoints -------------------------------------------------------------------------------
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# Add buffers on Endpoints (can be used to improve timings)
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class BufferizeEndpoints(ModuleTransformer):
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@ -765,6 +775,3 @@ class BufferizeEndpoints(ModuleTransformer):
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setattr(submodule, name, buf.source)
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else:
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raise ValueError
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# XXX
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