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integration/soc/add_adapter: rename is_master to direction.
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parent
57390666d8
commit
59d88a880c
1 changed files with 9 additions and 5 deletions
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@ -282,7 +282,8 @@ class SoCBusHandler(Module):
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return is_io
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# Add Master/Slave -----------------------------------------------------------------------------
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def add_adapter(self, name, interface, is_master):
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def add_adapter(self, name, interface, direction="m2s"):
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assert direction in ["m2s", "s2m"]
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if interface.data_width != self.data_width:
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self.logger.info("{} Bus {} from {}-bit to {}-bit.".format(
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colorer(name),
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@ -290,8 +291,11 @@ class SoCBusHandler(Module):
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colorer(interface.data_width),
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colorer(self.data_width)))
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new_interface = wishbone.Interface(data_width=self.data_width)
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args = (interface, new_interface) if is_master else (new_interface, interface)
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self.submodules += wishbone.Converter(*args)
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if direction == "m2s":
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converter = wishbone.Converter(master=interface, slave=new_interface)
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if direction == "s2m":
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converter = wishbone.Converter(master=new_interface, slave=interface)
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self.submodules += converter
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return new_interface
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else:
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return interface
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@ -305,7 +309,7 @@ class SoCBusHandler(Module):
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colorer("already declared", color="red")))
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self.logger.error(self)
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raise
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master = self.add_adapter(name, master, True)
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master = self.add_adapter(name, master, "m2s")
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self.masters[name] = master
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self.logger.info("{} {} as Bus Master.".format(
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colorer(name, color="underline"),
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@ -337,7 +341,7 @@ class SoCBusHandler(Module):
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colorer("already declared", color="red")))
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self.logger.error(self)
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raise
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slave = self.add_adapter(name, slave, False)
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slave = self.add_adapter(name, slave, "s2m")
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self.slaves[name] = slave
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self.logger.info("{} {} as Bus Slave.".format(
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colorer(name, color="underline"),
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