core/cpu/vexriscv/core: improve indentation

This commit is contained in:
Florent Kermarrec 2018-07-05 16:51:40 +02:00
parent 6068f6ce9c
commit 59fa71593d
1 changed files with 28 additions and 28 deletions

View File

@ -171,37 +171,37 @@ class VexRiscv(Module, AutoCSR):
self.comb += self.debug_reset.eq(0) self.comb += self.debug_reset.eq(0)
self.specials += Instance("VexRiscv", self.specials += Instance("VexRiscv",
i_clk=ClockSignal(), i_clk=ClockSignal(),
i_reset=i_reset, i_reset=i_reset,
i_externalResetVector=cpu_reset_address, i_externalResetVector=cpu_reset_address,
i_externalInterruptArray=self.interrupt, i_externalInterruptArray=self.interrupt,
i_timerInterrupt=0, i_timerInterrupt=0,
o_iBusWishbone_ADR=i.adr, o_iBusWishbone_ADR=i.adr,
o_iBusWishbone_DAT_MOSI=i.dat_w, o_iBusWishbone_DAT_MOSI=i.dat_w,
o_iBusWishbone_SEL=i.sel, o_iBusWishbone_SEL=i.sel,
o_iBusWishbone_CYC=i.cyc, o_iBusWishbone_CYC=i.cyc,
o_iBusWishbone_STB=i.stb, o_iBusWishbone_STB=i.stb,
o_iBusWishbone_WE=i.we, o_iBusWishbone_WE=i.we,
o_iBusWishbone_CTI=i.cti, o_iBusWishbone_CTI=i.cti,
o_iBusWishbone_BTE=i.bte, o_iBusWishbone_BTE=i.bte,
i_iBusWishbone_DAT_MISO=i.dat_r, i_iBusWishbone_DAT_MISO=i.dat_r,
i_iBusWishbone_ACK=i.ack, i_iBusWishbone_ACK=i.ack,
i_iBusWishbone_ERR=i.err, i_iBusWishbone_ERR=i.err,
o_dBusWishbone_ADR=d.adr, o_dBusWishbone_ADR=d.adr,
o_dBusWishbone_DAT_MOSI=d.dat_w, o_dBusWishbone_DAT_MOSI=d.dat_w,
o_dBusWishbone_SEL=d.sel, o_dBusWishbone_SEL=d.sel,
o_dBusWishbone_CYC=d.cyc, o_dBusWishbone_CYC=d.cyc,
o_dBusWishbone_STB=d.stb, o_dBusWishbone_STB=d.stb,
o_dBusWishbone_WE=d.we, o_dBusWishbone_WE=d.we,
o_dBusWishbone_CTI=d.cti, o_dBusWishbone_CTI=d.cti,
o_dBusWishbone_BTE=d.bte, o_dBusWishbone_BTE=d.bte,
i_dBusWishbone_DAT_MISO=d.dat_r, i_dBusWishbone_DAT_MISO=d.dat_r,
i_dBusWishbone_ACK=d.ack, i_dBusWishbone_ACK=d.ack,
i_dBusWishbone_ERR=d.err, i_dBusWishbone_ERR=d.err,
**kwargs) **kwargs)
# add verilog sources # add verilog sources
self.add_sources(platform, source_file) self.add_sources(platform, source_file)