fhdl/verilog: Remove display_run (not used in LiteX).
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@ -351,10 +351,7 @@ def _print_module(f, ios, name, ns, attr_translate,
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# Print Combinatorial Logic (Simulation) -----------------------------------------------------------
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def _print_combinatorial_logic_sim(f, ns,
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display_run,
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dummy_signal,
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blocking_assign):
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def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
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r = ""
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if f.comb:
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if dummy_signal:
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@ -392,8 +389,6 @@ def _print_combinatorial_logic_sim(f, ns,
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r += syn_on
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r += "always @(*) begin\n"
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if display_run:
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r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
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if blocking_assign:
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r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n"
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r += _print_node(ns, _AT_BLOCKING, 1, stmts, t)
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@ -471,7 +466,6 @@ def convert(f, ios=set(), name="top",
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special_overrides = dict(),
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attr_translate = DummyAttrTranslate(),
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create_clock_domains = True,
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display_run = False,
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reg_initialization = True,
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dummy_signal = True,
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blocking_assign = False,
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@ -549,7 +543,6 @@ def convert(f, ios=set(), name="top",
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)
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else:
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verilog += _print_combinatorial_logic_sim(f, ns,
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display_run = display_run,
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dummy_signal = dummy_signal,
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blocking_assign = blocking_assign
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)
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