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fhdl/verilog: Remove display_run (not used in LiteX).

This commit is contained in:
Florent Kermarrec 2021-10-15 14:43:42 +02:00
parent 8aad25ae2b
commit 5a2399b037
1 changed files with 1 additions and 8 deletions
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9
litex/gen/fhdl/verilog.py
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@ -351,10 +351,7 @@ def _print_module(f, ios, name, ns, attr_translate,
# Print Combinatorial Logic (Simulation) ----------------------------------------------------------- # Print Combinatorial Logic (Simulation) -----------------------------------------------------------
def _print_combinatorial_logic_sim(f, ns, def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
display_run,
dummy_signal,
blocking_assign):
r = "" r = ""
if f.comb: if f.comb:
if dummy_signal: if dummy_signal:
@ -392,8 +389,6 @@ def _print_combinatorial_logic_sim(f, ns,
r += syn_on r += syn_on
r += "always @(*) begin\n" r += "always @(*) begin\n"
if display_run:
r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
if blocking_assign: if blocking_assign:
r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n" r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_BLOCKING, 1, stmts, t) r += _print_node(ns, _AT_BLOCKING, 1, stmts, t)
@ -471,7 +466,6 @@ def convert(f, ios=set(), name="top",
special_overrides = dict(), special_overrides = dict(),
attr_translate = DummyAttrTranslate(), attr_translate = DummyAttrTranslate(),
create_clock_domains = True, create_clock_domains = True,
display_run = False,
reg_initialization = True, reg_initialization = True,
dummy_signal = True, dummy_signal = True,
blocking_assign = False, blocking_assign = False,
@ -549,7 +543,6 @@ def convert(f, ios=set(), name="top",
) )
else: else:
verilog += _print_combinatorial_logic_sim(f, ns, verilog += _print_combinatorial_logic_sim(f, ns,
display_run = display_run,
dummy_signal = dummy_signal, dummy_signal = dummy_signal,
blocking_assign = blocking_assign blocking_assign = blocking_assign
) )