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soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read. 

When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
This commit is contained in:
Florent Kermarrec 2020-01-16 19:45:41 +01:00
parent 862e784eae
commit 5aa516cb8d
1 changed files with 4 additions and 3 deletions
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7
litex/soc/cores/uart.py
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@ -191,7 +191,8 @@ class UART(Module, AutoCSR, UARTInterface):
def __init__(self, phy=None, def __init__(self, phy=None,
tx_fifo_depth=16, tx_fifo_depth=16,
rx_fifo_depth=16, rx_fifo_depth=16,
phy_cd="sys"): rx_fifo_rx_we=False,
phy_cd="sys",):
self._rxtx = CSR(8) self._rxtx = CSR(8)
self._txfull = CSRStatus() self._txfull = CSRStatus()
self._rxempty = CSRStatus() self._rxempty = CSRStatus()
@ -233,7 +234,7 @@ class UART(Module, AutoCSR, UARTInterface):
self.sink.connect(rx_fifo.sink), self.sink.connect(rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.valid), self._rxempty.status.eq(~rx_fifo.source.valid),
self._rxtx.w.eq(rx_fifo.source.data), self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ready.eq(self.ev.rx.clear), rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)),
# Generate RX IRQ when tx_fifo becomes non-empty # Generate RX IRQ when tx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_fifo.source.valid) self.ev.rx.trigger.eq(~rx_fifo.source.valid)
] ]
@ -271,7 +272,7 @@ class UARTCrossover(UART):
def __init__(self, **kwargs): def __init__(self, **kwargs):
assert kwargs.get("phy", None) == None assert kwargs.get("phy", None) == None
UART.__init__(self, **kwargs) UART.__init__(self, **kwargs)
self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2) self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=False)
self.comb += [ self.comb += [
self.source.connect(self.xover.sink), self.source.connect(self.xover.sink),
self.xover.source.connect(self.sink) self.xover.source.connect(self.sink)