test/spi_mmap: be less verbose
don't print miso/mosi changes with -v
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c2da8de7b0
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5ae098ebc6
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@ -50,6 +50,14 @@ def vprint(*args):
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print(*args)
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print(*args)
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def vvprint(*args):
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global verbose
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if verbose is None:
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verbose = unittest_verbosity()
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if verbose > 2:
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print(*args)
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class TestSPIMMAP(unittest.TestCase):
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class TestSPIMMAP(unittest.TestCase):
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def test_spi_master(self):
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def test_spi_master(self):
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pads = Record([("clk", 1), ("cs_n", 4), ("mosi", 1), ("miso", 1)])
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pads = Record([("clk", 1), ("cs_n", 4), ("mosi", 1), ("miso", 1)])
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@ -219,9 +227,9 @@ class TestSPIMMAP(unittest.TestCase):
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if tx_empty != (tx_empty := (yield dut_tx_status.empty)):
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if tx_empty != (tx_empty := (yield dut_tx_status.empty)):
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vprint(f"tx_empty:{tx_empty}")
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vprint(f"tx_empty:{tx_empty}")
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if mosi != (mosi := (yield dut.tx_rx_engine.spi.mosi)):
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if mosi != (mosi := (yield dut.tx_rx_engine.spi.mosi)):
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vprint(f"mosi => {mosi:0{width}x}")
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vvprint(f"mosi => {mosi:0{width}x}")
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if miso != (miso := (yield dut.tx_rx_engine.spi.miso)):
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if miso != (miso := (yield dut.tx_rx_engine.spi.miso)):
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vprint(f"miso <= {miso:0{width}x}")
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vvprint(f"miso <= {miso:0{width}x}")
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yield
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yield
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yield
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yield
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