Remove ASMI
This commit is contained in:
Sebastien Bourdeauducq
parent
faa8b7c49a
commit
5b36f688ea
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@ -1,163 +0,0 @@
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from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.genlib.buffers import ReorderBuffer
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class SequentialReader(Module):
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def __init__(self, port):
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assert(len(port.slots) == 1)
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self.address = Sink([("a", port.hub.aw)])
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self.data = Source([("d", port.hub.dw)])
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self.busy = Signal()
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###
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sample = Signal()
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data_reg_loaded = Signal()
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data_reg = Signal(port.hub.dw)
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accept_new = Signal()
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# We check that len(port.slots) == 1
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# and therefore we can assume that port.ack
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# goes low until the data phase.
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self.comb += [
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self.busy.eq(~data_reg_loaded | ~port.ack),
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port.adr.eq(self.address.payload.a),
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port.we.eq(0),
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accept_new.eq(~data_reg_loaded | self.data.ack),
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port.stb.eq(self.address.stb & accept_new),
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self.address.ack.eq(port.ack & accept_new),
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self.data.stb.eq(data_reg_loaded),
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self.data.payload.d.eq(data_reg)
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]
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self.sync += [
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If(self.data.ack, data_reg_loaded.eq(0)),
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If(sample,
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data_reg_loaded.eq(1),
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data_reg.eq(port.dat_r)
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),
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sample.eq(port.get_call_expression())
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]
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class OOOReader(Module):
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def __init__(self, port):
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assert(len(port.slots) > 1)
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self.address = Sink([("a", port.hub.aw)])
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self.data = Source([("d", port.hub.dw)])
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self.busy = Signal() # TODO: drive busy
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###
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tag_width = flen(port.tag_call)
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data_width = port.hub.dw
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depth = len(port.slots)
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rob = ReorderBuffer(tag_width, data_width, depth)
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self.submodules += rob
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self.comb += [
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port.adr.eq(self.address.payload.a),
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port.we.eq(0),
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port.stb.eq(self.address.stb & rob.can_issue),
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self.address.ack.eq(port.ack & rob.can_issue),
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rob.issue.eq(self.address.stb & port.ack),
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rob.tag_issue.eq(port.base + port.tag_issue),
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rob.data_call.eq(port.dat_r),
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self.data.stb.eq(rob.can_read),
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rob.read.eq(self.data.ack),
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self.data.payload.d.eq(rob.data_read)
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]
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self.sync += [
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# Data is announced one cycle in advance.
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# Register the call to synchronize it with the data signal.
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rob.call.eq(port.call),
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rob.tag_call.eq(port.tag_call)
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]
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class SequentialWriter(Module):
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def __init__(self, port):
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assert(len(port.slots) == 1)
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self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
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self.busy = Signal()
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###
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data_reg = Signal(port.hub.dw)
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self.comb += [
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port.adr.eq(self.address_data.payload.a),
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port.we.eq(1),
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port.stb.eq(self.address_data.stb),
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self.address_data.ack.eq(port.ack),
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port.dat_wm.eq(0)
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]
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self.sync += [
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port.dat_w.eq(0),
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If(port.get_call_expression(),
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self.busy.eq(0),
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port.dat_w.eq(data_reg)
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),
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If(self.address_data.stb & self.address_data.ack,
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self.busy.eq(1),
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data_reg.eq(self.address_data.payload.d)
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)
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]
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class _WriteSlot(Module):
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def __init__(self, port, load_data, n):
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self.busy = Signal()
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###
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drive_data = Signal()
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data_reg = Signal(port.hub.dw)
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self.comb += [
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If(drive_data, port.dat_w.eq(data_reg)),
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port.dat_wm.eq(0)
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]
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self.sync += [
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drive_data.eq(0),
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If(port.get_call_expression(n),
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self.busy.eq(0),
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drive_data.eq(1)
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),
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If(port.stb & port.ack & (port.tag_issue == n),
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self.busy.eq(1),
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data_reg.eq(load_data)
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),
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]
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class OOOWriter(Module):
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def __init__(self, port):
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assert(len(port.slots) > 1)
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self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
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self.busy = Signal()
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###
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self.comb += [
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port.adr.eq(self.address_data.payload.a),
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port.we.eq(1),
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port.stb.eq(self.address_data.stb),
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self.address_data.ack.eq(port.ack)
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]
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busy = 0
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for i in range(len(port.slots)):
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write_slot = _WriteSlot(port, self.address_data.payload.d, i)
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self.submodules += write_slot
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busy = busy | write_slot.busy
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self.comb += self.busy.eq(busy)
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def Reader(port):
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if len(port.slots) == 1:
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return SequentialReader(port)
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else:
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return OOOReader(port)
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def Writer(port):
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if len(port.slots) == 1:
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return SequentialWriter(port)
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else:
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return OOOWriter(port)
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@ -1,304 +0,0 @@
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from migen.fhdl.std import *
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from migen.fhdl.module import FinalizeError
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from migen.genlib.misc import optree
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from migen.genlib import roundrobin
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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(SLOT_EMPTY, SLOT_PENDING, SLOT_PROCESSING) = range(3)
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class Slot(Module):
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def __init__(self, aw, time):
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self.time = time
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self.state = Signal(2)
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self.we = Signal()
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self.adr = Signal(aw)
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if self.time:
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self.mature = Signal()
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self.allocate = Signal()
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self.allocate_we = Signal()
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self.allocate_adr = Signal(aw)
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self.process = Signal()
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self.call = Signal()
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###
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self.sync += [
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If(self.allocate,
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self.state.eq(SLOT_PENDING),
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self.we.eq(self.allocate_we),
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self.adr.eq(self.allocate_adr)
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),
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If(self.process, self.state.eq(SLOT_PROCESSING)),
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If(self.call, self.state.eq(SLOT_EMPTY))
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]
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if self.time:
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counter = Signal(max=self.time+1)
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self.comb += self.mature.eq(counter == 0)
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self.sync += [
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If(self.allocate,
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counter.eq(self.time)
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).Elif(counter != 0,
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counter.eq(counter - 1)
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)
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]
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class Port(Module):
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def __init__(self, hub, base, nslots):
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self.hub = hub
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self.base = base
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self.submodules.slots = [Slot(self.hub.aw, self.hub.time) for i in range(nslots)]
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# request issuance
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self.adr = Signal(self.hub.aw)
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self.we = Signal()
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self.stb = Signal()
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# tag_issue is created by finalize()
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self.ack = Signal()
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# request completion
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self.call = Signal()
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# tag_call is created by finalize()
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self.dat_r = Signal(self.hub.dw)
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self.dat_w = Signal(self.hub.dw)
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self.dat_wm = Signal(self.hub.dw//8)
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def do_finalize(self):
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nslots = len(self.slots)
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if nslots > 1:
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self.tag_issue = Signal(max=nslots)
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self.tag_call = Signal(self.hub.tagbits)
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# allocate
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for s in self.slots:
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self.comb += [
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s.allocate_we.eq(self.we),
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s.allocate_adr.eq(self.adr)
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]
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choose_slot = None
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needs_tags = len(self.slots) > 1
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for n, s in reversed(list(enumerate(self.slots))):
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choose_slot = If(s.state == SLOT_EMPTY,
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s.allocate.eq(self.stb),
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self.tag_issue.eq(n) if needs_tags else None
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).Else(choose_slot)
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self.comb += choose_slot
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self.comb += self.ack.eq(optree("|",
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[s.state == SLOT_EMPTY for s in self.slots]))
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# call
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self.comb += [s.call.eq(self.get_call_expression(n))
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for n, s in enumerate(self.slots)]
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def get_call_expression(self, slotn=0):
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if not self.finalized:
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raise FinalizeError
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return self.call \
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& (self.tag_call == (self.base + slotn))
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class Hub(Module):
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def __init__(self, aw, dw, time=0):
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self.aw = aw
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self.dw = dw
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self.time = time
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self.ports = []
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self._next_base = 0
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self.tagbits = 0
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self.call = Signal()
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# tag_call is created by do_finalize()
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self.dat_r = Signal(self.dw)
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self.dat_w = Signal(self.dw)
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self.dat_wm = Signal(self.dw//8)
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def get_port(self, nslots=1):
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if self.finalized:
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raise FinalizeError
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new_port = Port(self, self._next_base, nslots)
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self._next_base += nslots
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self.tagbits = bits_for(self._next_base-1)
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self.ports.append(new_port)
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self.submodules += new_port
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return new_port
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def do_finalize(self):
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self.tag_call = Signal(self.tagbits)
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for port in self.ports:
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self.comb += [
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port.call.eq(self.call),
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port.tag_call.eq(self.tag_call),
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port.dat_r.eq(self.dat_r)
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]
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self.comb += [
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self.dat_w.eq(optree("|", [port.dat_w for port in self.ports])),
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self.dat_wm.eq(optree("|", [port.dat_wm for port in self.ports]))
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]
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def get_slots(self):
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if not self.finalized:
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raise FinalizeError
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return sum([port.slots for port in self.ports], [])
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class Tap(Module):
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def __init__(self, hub, handler=print):
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self.hub = hub
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self.handler = handler
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self.tag_to_transaction = dict()
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self.transaction = None
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def do_simulation(self, s):
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hub = Proxy(s, self.hub)
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# Pull any data announced in the previous cycle.
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if isinstance(self.transaction, TWrite):
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self.transaction.data = hub.dat_w
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self.transaction.sel = ~hub.dat_wm
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self.handler(self.transaction)
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self.transaction = None
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if isinstance(self.transaction, TRead):
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self.transaction.data = hub.dat_r
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self.handler(self.transaction)
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self.transaction = None
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# Tag issue. Transaction objects are created here
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# and placed into the tag_to_transaction dictionary.
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for tag, slot in enumerate(self.hub.get_slots()):
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if s.rd(slot.allocate):
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adr = s.rd(slot.allocate_adr)
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we = s.rd(slot.allocate_we)
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if we:
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transaction = TWrite(adr)
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else:
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transaction = TRead(adr)
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transaction.latency = s.cycle_counter
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self.tag_to_transaction[tag] = transaction
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# Tag call.
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if hub.call:
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transaction = self.tag_to_transaction[hub.tag_call]
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transaction.latency = s.cycle_counter - transaction.latency + 1
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self.transaction = transaction
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class Initiator(Module):
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def __init__(self, generator, port):
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self.generator = generator
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self.port = port
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self.done = False
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self._exe = None
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def _execute(self, s, generator, port):
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while True:
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transaction = next(generator)
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transaction_start = s.cycle_counter
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if transaction is None:
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yield
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else:
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# tag phase
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s.wr(port.adr, transaction.address)
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if isinstance(transaction, TWrite):
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s.wr(port.we, 1)
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else:
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s.wr(port.we, 0)
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s.wr(port.stb, 1)
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yield
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while not s.rd(port.ack):
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yield
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if hasattr(port, "tag_issue"):
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tag = s.rd(port.tag_issue)
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else:
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tag = 0
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tag += port.base
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s.wr(port.stb, 0)
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# data phase
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while not (s.rd(port.call) and (s.rd(port.tag_call) == tag)):
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yield
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if isinstance(transaction, TWrite):
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s.wr(port.dat_w, transaction.data)
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s.wr(port.dat_wm, ~transaction.sel)
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yield
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s.wr(port.dat_w, 0)
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s.wr(port.dat_wm, 0)
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else:
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yield
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transaction.data = s.rd(port.dat_r)
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transaction.latency = s.cycle_counter - transaction_start - 1
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def do_simulation(self, s):
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if not self.done:
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if self._exe is None:
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self._exe = self._execute(s, self.generator, self.port)
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try:
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next(self._exe)
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except StopIteration:
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self.done = True
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class TargetModel:
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def __init__(self):
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self.last_slot = 0
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def read(self, address):
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return 0
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def write(self, address, data, mask):
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pass
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# Round-robin scheduling.
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def select_slot(self, pending_slots):
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if not pending_slots:
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return -1
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self.last_slot += 1
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if self.last_slot > max(pending_slots):
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self.last_slot = 0
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while self.last_slot not in pending_slots:
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self.last_slot += 1
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return self.last_slot
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class Target(Module):
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def __init__(self, model, hub):
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self.model = model
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self.hub = hub
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self._calling_tag = -1
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self._write_request_d = -1
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self._write_request = -1
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self._read_request = -1
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def do_simulation(self, s):
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slots = self.hub.get_slots()
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# Data I/O
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if self._write_request >= 0:
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self.model.write(self._write_request,
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s.rd(self.hub.dat_w), s.rd(self.hub.dat_wm))
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if self._read_request >= 0:
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s.wr(self.hub.dat_r, self.model.read(self._read_request))
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# Request pipeline
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self._read_request = -1
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self._write_request = self._write_request_d
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self._write_request_d = -1
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# Examine pending slots and possibly choose one.
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# Note that we do not use the SLOT_PROCESSING state here.
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# Selected slots are immediately called.
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pending_slots = set()
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for tag, slot in enumerate(slots):
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if tag != self._calling_tag and s.rd(slot.state) == SLOT_PENDING:
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pending_slots.add(tag)
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slot_to_call = self.model.select_slot(pending_slots)
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# Call slot.
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if slot_to_call >= 0:
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slot = slots[slot_to_call]
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s.wr(self.hub.call, 1)
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s.wr(self.hub.tag_call, slot_to_call)
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self._calling_tag = slot_to_call
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if s.rd(slot.we):
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self._write_request_d = s.rd(slot.adr)
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else:
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self._read_request = s.rd(slot.adr)
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else:
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s.wr(self.hub.call, 0)
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self._calling_tag = -1
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@ -1,137 +0,0 @@
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import split, displacer, chooser
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from migen.genlib.record import Record, layout_len
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# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
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class WB2ASMI:
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def __init__(self, cachesize, asmiport):
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self.wishbone = wishbone.Interface()
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self.cachesize = cachesize
|
||||
self.asmiport = asmiport
|
||||
if len(self.asmiport.slots) != 1:
|
||||
raise ValueError("ASMI port must have 1 slot")
|
||||
if self.asmiport.hub.dw <= 32:
|
||||
raise ValueError("ASMI data width must be strictly larger than 32")
|
||||
if (self.asmiport.hub.dw % 32) != 0:
|
||||
raise ValueError("ASMI data width must be a multiple of 32")
|
||||
|
||||
def get_fragment(self):
|
||||
comb = []
|
||||
sync = []
|
||||
|
||||
aaw = self.asmiport.hub.aw
|
||||
adw = self.asmiport.hub.dw
|
||||
|
||||
# Split address:
|
||||
# TAG | LINE NUMBER | LINE OFFSET
|
||||
offsetbits = log2_int(adw//32)
|
||||
addressbits = aaw + offsetbits
|
||||
linebits = log2_int(self.cachesize) - offsetbits
|
||||
tagbits = addressbits - linebits
|
||||
adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
|
||||
|
||||
# Data memory
|
||||
data_mem = Memory(adw, 2**linebits)
|
||||
data_port = data_mem.get_port(write_capable=True, we_granularity=8)
|
||||
|
||||
write_from_asmi = Signal()
|
||||
write_to_asmi = Signal()
|
||||
adr_offset_r = Signal(offsetbits)
|
||||
comb += [
|
||||
data_port.adr.eq(adr_line),
|
||||
If(write_from_asmi,
|
||||
data_port.dat_w.eq(self.asmiport.dat_r),
|
||||
data_port.we.eq(Replicate(1, adw//8))
|
||||
).Else(
|
||||
data_port.dat_w.eq(Replicate(self.wishbone.dat_w, adw//32)),
|
||||
If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
|
||||
displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
|
||||
)
|
||||
),
|
||||
If(write_to_asmi, self.asmiport.dat_w.eq(data_port.dat_r)),
|
||||
self.asmiport.dat_wm.eq(0),
|
||||
chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True)
|
||||
]
|
||||
sync += [
|
||||
adr_offset_r.eq(adr_offset)
|
||||
]
|
||||
|
||||
# Tag memory
|
||||
tag_layout = [("tag", tagbits), ("dirty", 1)]
|
||||
tag_mem = Memory(layout_len(tag_layout), 2**linebits)
|
||||
tag_port = tag_mem.get_port(write_capable=True)
|
||||
tag_do = Record(tag_layout)
|
||||
tag_di = Record(tag_layout)
|
||||
comb += [
|
||||
tag_do.raw_bits().eq(tag_port.dat_r),
|
||||
tag_port.dat_w.eq(tag_di.raw_bits())
|
||||
]
|
||||
|
||||
comb += [
|
||||
tag_port.adr.eq(adr_line),
|
||||
tag_di.tag.eq(adr_tag),
|
||||
self.asmiport.adr.eq(Cat(adr_line, tag_do.tag))
|
||||
]
|
||||
|
||||
# Control FSM
|
||||
write_to_asmi_pre = Signal()
|
||||
sync.append(write_to_asmi.eq(write_to_asmi_pre))
|
||||
|
||||
fsm = FSM()
|
||||
|
||||
fsm.act("IDLE",
|
||||
If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT"))
|
||||
)
|
||||
fsm.act("TEST_HIT",
|
||||
If(tag_do.tag == adr_tag,
|
||||
self.wishbone.ack.eq(1),
|
||||
If(self.wishbone.we,
|
||||
tag_di.dirty.eq(1),
|
||||
tag_port.we.eq(1)
|
||||
),
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
If(tag_do.dirty,
|
||||
NextState("EVICT_ISSUE")
|
||||
).Else(
|
||||
NextState("REFILL_WRTAG")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("EVICT_ISSUE",
|
||||
self.asmiport.stb.eq(1),
|
||||
self.asmiport.we.eq(1),
|
||||
If(self.asmiport.ack, NextState("EVICT_WAIT"))
|
||||
)
|
||||
fsm.act("EVICT_WAIT",
|
||||
# Data is actually sampled by the memory controller in the next state.
|
||||
# But since the data memory has one cycle latency, it gets the data
|
||||
# at the address given during this cycle.
|
||||
If(self.asmiport.get_call_expression(),
|
||||
write_to_asmi_pre.eq(1),
|
||||
NextState("REFILL_WRTAG")
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("REFILL_WRTAG",
|
||||
# Write the tag first to set the ASMI address
|
||||
tag_port.we.eq(1),
|
||||
NextState("REFILL_ISSUE")
|
||||
)
|
||||
fsm.act("REFILL_ISSUE",
|
||||
self.asmiport.stb.eq(1),
|
||||
If(self.asmiport.ack, NextState("REFILL_WAIT"))
|
||||
)
|
||||
fsm.act("REFILL_WAIT",
|
||||
If(self.asmiport.get_call_expression(), NextState("REFILL_COMPLETE"))
|
||||
)
|
||||
fsm.act("REFILL_COMPLETE",
|
||||
write_from_asmi.eq(1),
|
||||
NextState("TEST_HIT")
|
||||
)
|
||||
|
||||
return Fragment(comb, sync, specials={data_mem, tag_mem, data_port, tag_port}) \
|
||||
+ fsm.get_fragment()
|
||||
Loading…
Reference in New Issue