make packetizer/depacketizer generic and use it for all layers
This commit is contained in:
parent
dc5e1aa1ad
commit
5b37068393
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@ -0,0 +1,19 @@
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from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthARPDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_mac_description(8),
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eth_arp_description(8),
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arp_header,
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arp_header_length)
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class LiteEthARPPacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_arp_description(8),
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eth_mac_description(8),
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arp_header,
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arp_header_length)
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@ -1,7 +1,7 @@
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from collections import OrderedDict
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from collections import OrderedDict
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from migen.fhdl.std import *
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from migen.fhdl.std import *
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from migen.fhdl.std import *
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from migen.fhdl.decorators import ModuleDecorator
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.record import *
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from migen.genlib.record import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.fsm import FSM, NextState
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@ -160,3 +160,4 @@ class BufferizeEndpoints(ModuleDecorator):
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self.submodules += buf
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self.submodules += buf
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self.comb += Record.connect(source, buf.d)
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self.comb += Record.connect(source, buf.d)
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setattr(self, name, buf.q)
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setattr(self, name, buf.q)
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@ -1,5 +1,3 @@
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import math
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from liteeth.common import *
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from liteeth.common import *
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def _decode_header(h_dict, h_signal, obj):
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def _decode_header(h_dict, h_signal, obj):
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@ -10,14 +8,14 @@ def _decode_header(h_dict, h_signal, obj):
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r.append(getattr(obj, k).eq(h_signal[start:end]))
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r.append(getattr(obj, k).eq(h_signal[start:end]))
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return r
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return r
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class LiteEthMACDepacketizer(Module):
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class LiteEthDepacketizer(Module):
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def __init__(self):
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def __init__(self, sink_description, source_description, header_type, header_length):
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self.sink = sink = Sink(eth_mac_description(8))
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self.sink = sink = Sink(sink_description)
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self.source = source = Source(eth_phy_description(8))
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self.source = source = Source(source_description)
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###
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###
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shift = Signal()
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shift = Signal()
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header = Signal(mac_header_length*8)
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header = Signal(header_length*8)
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counter = Counter(max=mac_header_length)
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counter = Counter(max=header_length)
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self.submodules += counter
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self.submodules += counter
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fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="IDLE")
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@ -36,7 +34,7 @@ class LiteEthMACDepacketizer(Module):
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If(sink.stb,
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If(sink.stb,
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counter.ce.eq(1),
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counter.ce.eq(1),
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shift.eq(1),
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shift.eq(1),
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If(counter.value == mac_header_length-2,
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If(counter.value == header_length-2,
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NextState("COPY")
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NextState("COPY")
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)
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)
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)
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)
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@ -52,7 +50,7 @@ class LiteEthMACDepacketizer(Module):
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source.eop.eq(sink.eop),
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source.eop.eq(sink.eop),
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source.data.eq(sink.data),
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source.data.eq(sink.data),
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source.error.eq(sink.error),
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source.error.eq(sink.error),
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_decode_header(mac_header, header, source)
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_decode_header(header_type, header, source)
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]
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]
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fsm.act("COPY",
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fsm.act("COPY",
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sink.ack.eq(source.ack),
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sink.ack.eq(source.ack),
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@ -8,19 +8,19 @@ def _encode_header(h_dict, h_signal, obj):
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r.append(h_signal[start:end].eq(getattr(obj, k)))
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r.append(h_signal[start:end].eq(getattr(obj, k)))
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return r
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return r
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class LiteEthMACPacketizer(Module):
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class LiteEthPacketizer(Module):
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def __init__(self):
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def __init__(self, sink_description, source_description, header_type, header_length):
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self.sink = sink = Sink(eth_phy_description(8))
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self.sink = sink = Sink(sink_description)
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self.source = source = Source(eth_mac_description(8))
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self.source = source = Source(source_description)
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###
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###
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header = Signal(mac_header_length*8)
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header = Signal(header_length*8)
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header_reg = Signal(mac_header_length*8)
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header_reg = Signal(header_length*8)
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load = Signal()
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load = Signal()
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shift = Signal()
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shift = Signal()
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counter = Counter(max=mac_header_length)
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counter = Counter(max=header_length)
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self.submodules += counter
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self.submodules += counter
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self.comb += header.eq(_encode_header(mac_header, header, sink))
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self.comb += header.eq(_encode_header(header_type, header, sink))
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self.sync += [
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self.sync += [
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If(load,
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If(load,
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header_reg.eq(header)
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header_reg.eq(header)
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@ -53,7 +53,7 @@ class LiteEthMACPacketizer(Module):
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source.data.eq(header_reg[8:16]),
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source.data.eq(header_reg[8:16]),
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If(source.stb & source.ack,
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If(source.stb & source.ack,
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sink.ack.eq(1),
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sink.ack.eq(1),
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If(counter == mac_header_length-2,
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If(counter == header_length-2,
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NextState("COPY")
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NextState("COPY")
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)
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)
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)
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)
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@ -0,0 +1,19 @@
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from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_mac_description(8),
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eth_ipv4_description(8),
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ipv4_header,
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ipv4_header_length)
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class LiteEthIPV4Packetizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_ipv4_description(8),
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eth_mac_description(8),
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ipv4_header,
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ipv4_header_length)
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@ -1,6 +1,24 @@
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from liteeth.common import *
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from liteeth.common import *
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from liteeth.mac.core import LiteEthMACCore
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from liteeth.mac.core import LiteEthMACCore
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from liteeth.mac.frontend import wishbone
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from liteeth.mac.frontend import wishbone
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthMACDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_phy_description(8),
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eth_mac_description(8),
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mac_header,
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mac_header_length)
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class LiteEthMACPacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_mac_description(8),
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eth_phy_description(8),
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mac_header,
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mac_header_length)
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class LiteEthMAC(Module, AutoCSR):
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class LiteEthMAC(Module, AutoCSR):
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def __init__(self, phy, dw, interface="core", endianness="be",
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def __init__(self, phy, dw, interface="core", endianness="be",
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@ -15,11 +15,11 @@ class TB(Module):
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self.submodules.hostmac = mac.MAC(self.hostphy, debug=False, loopback=True)
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self.submodules.hostmac = mac.MAC(self.hostphy, debug=False, loopback=True)
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self.submodules.ethmac = LiteEthMAC(phy=self.hostphy, dw=32, interface="core", with_hw_preamble_crc=True)
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self.submodules.ethmac = LiteEthMAC(phy=self.hostphy, dw=32, interface="core", with_hw_preamble_crc=True)
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self.submodules.streamer = PacketStreamer(eth_mac_description(32), last_be=1)
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self.submodules.streamer = PacketStreamer(eth_phy_description(32), last_be=1)
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self.submodules.streamer_randomizer = AckRandomizer(eth_mac_description(32), level=50)
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self.submodules.streamer_randomizer = AckRandomizer(eth_phy_description(32), level=50)
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self.submodules.logger_randomizer = AckRandomizer(eth_mac_description(32), level=50)
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self.submodules.logger_randomizer = AckRandomizer(eth_phy_description(32), level=50)
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self.submodules.logger = PacketLogger(eth_mac_description(32))
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self.submodules.logger = PacketLogger(eth_phy_description(32))
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# use sys_clk for each clock_domain
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_rx = ClockDomain()
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@ -0,0 +1,19 @@
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from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthUDPDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_ipv4_description(8),
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eth_udp_description(8),
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udp_header,
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udp_header_length)
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class LiteEthUDPPacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_udp_description(8),
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eth_ipv4_description(8),
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udp_header,
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udp_header_length)
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