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soc_core: expose CSR paging

This commit is contained in:
Florent Kermarrec 2020-02-17 08:34:10 +01:00
parent 0497f3ca71
commit 5b3808cb81
1 changed files with 4 additions and 1 deletions
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5
litex/soc/integration/soc_core.py
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@ -78,6 +78,7 @@ class SoCCore(LiteXSoC):
csr_data_width = 8, csr_data_width = 8,
csr_alignment = 32, csr_alignment = 32,
csr_address_width = 14, csr_address_width = 14,
csr_paging = 0x800,
# Identifier parameters # Identifier parameters
ident = "", ident = "",
ident_version = False, ident_version = False,
@ -106,7 +107,7 @@ class SoCCore(LiteXSoC):
csr_data_width = csr_data_width, csr_data_width = csr_data_width,
csr_address_width = csr_address_width, csr_address_width = csr_address_width,
csr_alignment = csr_alignment, csr_alignment = csr_alignment,
csr_paging = 0x800, csr_paging = csr_paging,
csr_reserved_csrs = self.csr_map, csr_reserved_csrs = self.csr_map,
irq_n_irqs = 32, irq_n_irqs = 32,
@ -271,6 +272,8 @@ def soc_core_args(parser):
help="CSR bus data-width (8 or 32, default=8)") help="CSR bus data-width (8 or 32, default=8)")
parser.add_argument("--csr-address-width", default=14, type=int, parser.add_argument("--csr-address-width", default=14, type=int,
help="CSR bus address-width") help="CSR bus address-width")
parser.add_argument("--csr-paging", default=0x800, type=int,
help="CSR bus paging")
# Identifier parameters # Identifier parameters
parser.add_argument("--ident", default=None, type=str, parser.add_argument("--ident", default=None, type=str,
help="SoC identifier (default=\"\"") help="SoC identifier (default=\"\"")