software/liblitedram: Enable ECP5DDRPHY features on GW2DDRPHY (since very similar).
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@ -326,7 +326,7 @@ static unsigned int sdram_write_read_check_test_pattern(int module, unsigned int
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command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
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command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
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cdelay(15);
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cdelay(15);
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#ifdef SDRAM_PHY_ECP5DDRPHY
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#if defined(SDRAM_PHY_ECP5DDRPHY) || defined(SDRAM_PHY_GW2DDRPHY)
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ddrphy_burstdet_clr_write(1);
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ddrphy_burstdet_clr_write(1);
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#endif
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#endif
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@ -362,7 +362,7 @@ static unsigned int sdram_write_read_check_test_pattern(int module, unsigned int
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}
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}
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}
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}
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#ifdef SDRAM_PHY_ECP5DDRPHY
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#if defined(SDRAM_PHY_ECP5DDRPHY) || defined(SDRAM_PHY_GW2DDRPHY)
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if (((ddrphy_burstdet_seen_read() >> module) & 0x1) != 1)
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if (((ddrphy_burstdet_seen_read() >> module) & 0x1) != 1)
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errors += 1;
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errors += 1;
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#endif
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#endif
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@ -894,7 +894,7 @@ static void sdram_read_leveling_rst_delay(int module) {
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/* Un-select module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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ddrphy_dly_sel_write(0);
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#ifdef SDRAM_PHY_ECP5DDRPHY
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#if defined(SDRAM_PHY_ECP5DDRPHY) || defined(SDRAM_PHY_GW2DDRPHY)
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/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
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/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
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ddrphy_dly_sel_write(0xff);
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ddrphy_dly_sel_write(0xff);
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ddrphy_dly_sel_write(0);
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ddrphy_dly_sel_write(0);
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@ -911,7 +911,7 @@ static void sdram_read_leveling_inc_delay(int module) {
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/* Un-select module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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ddrphy_dly_sel_write(0);
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#ifdef SDRAM_PHY_ECP5DDRPHY
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#if defined(SDRAM_PHY_ECP5DDRPHY) || defined(SDRAM_PHY_GW2DDRPHY)
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/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
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/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
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ddrphy_dly_sel_write(0xff);
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ddrphy_dly_sel_write(0xff);
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ddrphy_dly_sel_write(0);
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ddrphy_dly_sel_write(0);
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