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liteXXX cores: update README and doc

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Florent Kermarrec 2015-02-28 18:13:57 +01:00
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64
misoclib/com/liteeth/README
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@ -3,8 +3,7 @@
/ /__/ / __/ -_) _// __/ _ \
/____/_/\__/\__/___/\__/_//_/
Copyright 2012-2015 / EnjoyDigital
florent@enjoy-digital.fr
Copyright 2012-2015 / EnjoyDigital / M-Labs Ltd
A small footprint and configurable Ethernet core
with UDP/IP hw stack and Etherbone frontend
@ -12,14 +11,14 @@
[> Doc
---------
HTML : www.enjoy-digital.fr/litex/liteeth/
PDF : www.enjoy-digital.fr/litex/liteeth.pdf
HTML : www.enjoy-digital.fr/liteeth/
PDF : www.enjoy-digital.fr/liteeth.pdf
[> Intro
---------
LiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of LiteX libraries whose aims are to lower entry level of
LiteEth is part of MiSoC libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
@ -33,9 +32,8 @@ LiteEth uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteEth can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteEth can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
[> Features
-----------
@ -64,53 +62,41 @@ devel [AT] lists.m-labs.hk.
python3 setup.py install
cd ..
Note: in case you have issues with Migen, please retry
with our fork at:
https://github.com/enjoy-digital/misoc
until new features are merged.
3. Obtain MiSoC:
git clone https://github.com/m-labs/misoc --recursive
3. Obtain LiteScope and install it:
git clone https://github.com/enjoy-digital/litescope
cd litescope
python3 setup.py install
cd ..
4. Build and load UDP loopback design (only for KC705 for now):
go to misoclib/com/liteeth/example_designs/
run ./make.py -t udp all load-bitstream
4. Obtain LiteEth
git clone https://github.com/enjoy-digital/liteeth
5. Build and load UDP loopback design (only for KC705 for now):
python3 make.py -t udp all
6. Test design (only for KC705 for now):
5. Test design (only for KC705 for now):
try to ping 192.168.1.40
go to ./test directory:
change com port in config.py to your com port
run make test_udp
go to [..]/example_designs/test/
run ./make.py udp
7. Build and load Etherbone design (only for KC705 for now):
python3 make.py -t etherbone all
6. Build and load Etherbone design (only for KC705 for now):
python3 make.py -t etherbone all load-bitstream
8. Test design (only for KC705 for now):
7. Test design (only for KC705 for now):
try to ping 192.168.1.40
go to ./test directory run:
run make test_etherbone
go to [..]/example_designs/test/
run ./make.py etherbone
[> Simulations:
Simulations are available in ./liteth/test/:
Simulations are available in misoclib/com/liteeth/test/:
- mac_core_tb
- mac_wishbone_tb
- arp_tb
- ip_tb
- icmp_tb
- udp_tb
All ethernet layers have their own model tested against real Ethernet dumps (dumps.py)
To run a simulation, move to ./liteeth/test and run:
All ethernet layers have their own model tested against real ethernet dumps (dumps.py)
To run a simulation, move to misoclib/com/liteeth/test/ and run:
make simulation_name
[> Tests :
An UDP loopback example is provided and be controlled with: ./test/test_udp.py
An Etherbone example with Wishbone SRAM is provided and can be controlled with:
./test/test_etherbone.py
An Etherbone example with Wishbone SRAM and an UDP loopback example are provided.
Please goto to Getting Started section to see how to run the tests.
[> License
-----------
@ -129,7 +115,7 @@ do them if possible:
--------------------------
We love open-source hardware and like sharing our designs with others.
LiteEth is developed and maintained by EnjoyDigital.
LiteEth is mainly developed and maintained by EnjoyDigital.
If you would like to know more about LiteEth or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard

39
misoclib/com/liteeth/doc/source/docs/getting_started/downloads.rst
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@ -3,41 +3,6 @@
====================
Download and install
====================
1. Install Python3 and your vendor's software
Please follow Getting started section of LiteEth README_.
2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- cd ..
.. note::
In case you have issues with Migen, please retry with our forks at:
https://github.com/enjoy-digital/migen
until new features are merged.
3. Obtain LiteScope and install it:
- git clone https://github.com/enjoy-digital/litescope
- cd litescope
- python3 setup.py install
- cd ..
4. Obtain LiteEth
- git clone https://github.com/enjoy-digital/liteeth
5. Build and load UDP loopback design (only for KC705 for now):
- python3 make.py -t udp all
6. Test design (only for KC705 for now):
- try to ping 192.168.1.40
- go to ./test directory:
- change com port in config.py to your com port
- run make test_udp
7. Build and load Etherbone design (only for KC705 for now):
- python3 make.py -t etherbone all
8. Test design (only for KC705 for now):
- try to ping 192.168.1.40
- go to ./test directory run:
- run make test_etherbone
.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/com/liteeth/README

9
misoclib/com/liteeth/doc/source/docs/intro/about.rst
View File

@ -6,7 +6,7 @@ About LiteEth
LiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of LiteX libraries whose aims are to lower entry level of
LiteEth is part of MiSoC libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
@ -20,9 +20,8 @@ LiteEth uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteEth can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteEth can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
.. _about-toolchain:
@ -43,7 +42,7 @@ Support and Consulting
======================
We love open-source hardware and like sharing our designs with others.
LiteEth is developed and maintained by EnjoyDigital.
LiteEth is mainly developed and maintained by EnjoyDigital.
If you would like to know more about LiteEth or if you are already a happy user
and would like to extend it for your needs, EnjoyDigital can provide standard

16
misoclib/com/liteusb/README
View File

@ -3,11 +3,10 @@
/ /__/ / __/ -_) /_/ /\ \/ _ |
/____/_/\__/\__/\____/___/____/
Copyright 2015 / EnjoyDigital
florent@enjoy-digital.fr
Copyright 2015 / EnjoyDigital / M-Labs Ltd
A small footprint and configurable USB core
powered by Migen
A small footprint and configurable USB core
powered by Migen
[> Doc
---------
@ -17,7 +16,7 @@ XXX
---------
LiteUSB provides a small footprint and configurable USB core.
LiteUSB is part of LiteX libraries whose aims are to lower entry level of
LiteUSB is part of MiSoC libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
@ -31,9 +30,8 @@ LiteUSB uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteUSB can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteUSB can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
[> Features
-----------
@ -78,7 +76,7 @@ do them if possible:
--------------------------
We love open-source hardware and like sharing our designs with others.
LiteUSB is developed and maintained by EnjoyDigital.
LiteUSB is mainly developed and maintained by EnjoyDigital.
If you would like to know more about LiteUSB or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard

51
misoclib/mem/litesata/README
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@ -10,15 +10,14 @@
[> Doc
---------
HTML : www.enjoy-digital.fr/litex/litesata/
PDF : www.enjoy-digital.fr/litex/litesata.pdf
HTML : www.enjoy-digital.fr/litesata/
PDF : www.enjoy-digital.fr/litesata.pdf
[> Intro
---------
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
FPGA cores by providing simple, elegant and efficient implementations of
LiteSATA is part of MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future
@ -34,9 +33,8 @@ LiteSATA uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteSATA can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteSATA can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
[> Features
-----------
@ -93,37 +91,22 @@ devel [AT] lists.m-labs.hk.
python3 setup.py install
cd ..
Note: in case you have issues with Migen, please retry
with our fork at:
https://github.com/enjoy-digital/misoc
until new features are merged.
3. Obtain LiteScope and install it:
git clone https://github.com/enjoy-digital/litescope
cd litescope
python3 setup.py install
cd ..
4. Obtain LiteSATA
git clone https://github.com/enjoy-digital/litesata
3. Obtain MiSoC:
git clone https://github.com/m-labs/misoc --recursive
5. Build and load BIST design (only for KC705 for now):
python3 make.py all (-s BISTSoCDevel to add LiteScopeLA)
go to misoclib/mem/litesata/example_designs/
run ./make.py all load-bitstream
6. Test design (only for KC705 for now):
go to ./test directory and run:
change com port in config.py to your com port
python3 bist.py
go to [..]/example_designs/test/
run ./make.py --port your_serial_port bist
7. Visualize Link Layer transactions (if BISTSoCDevel):
go to ./test directory and run:
python3 test_la.py [your_cond]
your_cond can be wr_cmd, id_cmd, rd_resp, ...
(open test_la.py to see all conditions or add yours)
8. If you only want to build the core and use it with your
regular design flow:
python3 make.py -t core build-core
7. If you only want to build the core and use it with your
regular design flow:
go to misoclib/mem/litesata/example_designs/
run ./make.py -t core build-core
You can customize the core in [..]/example_design/targets/core.py
[> Simulations:
Simulations are available in ./lib/sata/test:
@ -160,7 +143,7 @@ do them if possible:
--------------------------
We love open-source hardware and like sharing our designs with others.
LiteSATA is developed and maintained by EnjoyDigital.
LiteSATA is mainly developed and maintained by EnjoyDigital.
If you would like to know more about LiteSATA or if you are already a happy user
and would like to extend it for your needs, EnjoyDigital can provide standard

39
misoclib/mem/litesata/doc/source/docs/getting_started/downloads.rst
View File

@ -3,41 +3,6 @@
====================
Download and install
====================
1. Install Python3 and your vendor's software
Please follow Getting started section of LiteSATA README_.
2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- cd ..
.. note::
In case you have issues with Migen, please retry with our fork at:
https://github.com/enjoy-digital/migen
until new features are merged.
3. Obtain LiteScope and install it:
- git clone https://github.com/enjoy-digital/litescope
- cd litescope
- python3 setup.py install
- cd ..
4. Obtain LiteSATA
- git clone https://github.com/enjoy-digital/litesata
5. Build and load BIST design (only for KC705 for now):
- python3 make.py all
6. Test design (only for KC705 for now):
- go to ./test directory and run:
- python3 bist.py
7. Visualize Link Layer transactions (if BISTSoCDevel):
- go to ./test directory and run:
- python3 test_la.py [your_cond]
- your_cond can be wr_cmd, id_cmd, rd_resp, ...
(open test_la.py to see all conditions or add yours)
8. If you only want to build the core and use it with your
regular design flow:
- python3 make.py -t core build-core
.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/mem/litesata/README

8
misoclib/mem/litesata/doc/source/docs/intro/about.rst
View File

@ -6,8 +6,7 @@ About LiteSATA
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
FPGA cores by providing simple, elegant and efficient implementations of
LiteSATA is part of MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future
@ -23,9 +22,8 @@ LiteSATA uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteSATA can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteSATA can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
.. _about-toolchain:

39
misoclib/tools/litescope/README
View File

@ -3,16 +3,15 @@
/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
/____/_/\__/\__/___/\__/\___/ .__/\__/
/_/
Copyright 2012-2015 / EnjoyDigital
florent@enjoy-digital.fr
Copyright 2012-2015 / EnjoyDigital / M-Labs Ltd
A small footprint and configurable embedded FPGA
logic analyzer core powered by Migen
[> Doc
---------
HTML : www.enjoy-digital.fr/litex/litescope/
PDF : www.enjoy-digital.fr/litex/litescope.pdf
HTML : www.enjoy-digital.fr/litescope/
PDF : www.enjoy-digital.fr/litescope.pdf
[> Intro
---------
@ -20,7 +19,7 @@ LiteScope is a small footprint and configurable embedded logic analyzer that you
can use in your FPGA and aims to provide a free, portable and flexible
alternative to vendor's solutions!
LiteScope is part of LiteX libraries whose aims are to lower entry level of complex
LiteScope is part of MiSoC libraries whose aims are to lower entry level of complex
FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
@ -38,7 +37,7 @@ LiteScope can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteScope produces "vcd" files that can be read in your regular waveforms viewer.
LiteScope handles various export formats: .vcd, .sr(sigrok), .csv, .py...
Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
@ -53,8 +52,8 @@ external Rx/Tx pins to be ready to debug or control all your Wishbone peripheral
- Storage qualifier
- Data storage in block rams
- Bridges:
- UART2Wishbone
- Ethernet2Wishbone ("Etherbone")
- UART2Wishbone (provided by LiteScope)
- Ethernet2Wishbone ("Etherbone") (when used with LiteEth)
[> Possible improvements
-------------------------
@ -81,23 +80,23 @@ devel [AT] lists.m-labs.hk.
python3 setup.py install
cd ..
Note: in case you have issues with Migen, please retry
with our forks at:
https://github.com/enjoy-digital/migen
until new features are merged.
3. Obtain LiteScope and install it:
git clone https://github.com/enjoy-digital/litescope
3. Obtain MiSoC:
git clone https://github.com/m-labs/misoc --recursive
4. Build and load test design:
python3 make.py -s [platform] all
go to misoclib/tools/litescope/example_designs/
./make.py -p [your_platform] all load-bitstream
Supported platforms are the ones already supported by Mibuild:
de0nano, m1, mixxeo, kc705, zedboard...
5. Test design:
go to ./test directory and run:
python3 test_io.py
python3 test_la.py
go to [..]/example_designs/test/ and run:
./make.py --port your_serial_port io (will blink leds)
./make.py --port your_serial_port la (will capture counter)
tests can also be executed over Etherbone (provided with LiteEth):
./make.py --ip_address fpga_ip_address io
./make.py --ip_address fpga_ip_address la
[> Simulations:
XXX convert simulations
@ -122,7 +121,7 @@ do them if possible:
--------------------------
We love open-source hardware and like sharing our designs with others.
LiteScope is developed and maintained by EnjoyDigital.
LiteScope is mainly developed and maintained by EnjoyDigital.
If you would like to know more about LiteScope or if you are already a happy user
and would like to extend it for your needs, EnjoyDigital can provide standard

24
misoclib/tools/litescope/doc/source/docs/getting_started/downloads.rst
View File

@ -3,26 +3,6 @@
====================
Download and install
====================
1. Install Python3 and your vendor's software
Please follow Getting started section of LiteScop README_.
2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- cd ..
.. note::
In case you have issues with Migen, please retry with our forks at:
https://github.com/enjoy-digital/migen
until new features are merged.
3. Obtain LiteScope
- git clone https://github.com/enjoy-digital/litescope
4. Build and load example design:
- python3 make.py all
5. Test design:
- go to ./test directoryand run:
- python3 test_io.py
- python3 test_la.py
.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/tools/litescope/README

8
misoclib/tools/litescope/doc/source/docs/intro/about.rst
View File

@ -6,9 +6,9 @@ About LiteScope
LiteScope is a small footprint and configurable embedded logic analyzer that you
can use in your FPGA and aims to provide a free, portable and flexible
alternatve to vendor's solutions!
alternative to vendor's solutions!
LiteScope is part of LiteX libraries whose aims are to lower entry level of complex
LiteScope is part of MiSoC libraries whose aims are to lower entry level of complex
FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
@ -26,7 +26,7 @@ LiteScope can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteScope produces "vcd" files that can be read in your regular waveforms viewer.
LiteScope handles various export formats: .vcd, .sr(sigrok), .csv, .py...
Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
@ -59,7 +59,7 @@ Support and Consulting
======================
We love open-source hardware and like sharing our designs with others.
LiteScope is developed and maintained by EnjoyDigital.
LiteScope is mainly developed and maintained by EnjoyDigital.
If you would like to know more about LiteScope or if you are already a happy user
and would like to extend it for your needs, EnjoyDigital can provide standard