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fhdl: export log2_int

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This commit is contained in:
Sebastien Bourdeauducq 2012-03-14 12:19:42 +01:00
parent 97fece249d
commit 5c0cc6292c
2 changed files with 13 additions and 13 deletions
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15
migen/bus/wishbone2asmi.py
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@ -4,17 +4,6 @@ from migen.corelogic.fsm import FSM
from migen.corelogic.misc import split, displacer, chooser from migen.corelogic.misc import split, displacer, chooser
from migen.corelogic.record import Record from migen.corelogic.record import Record
def _log2_int(n):
l = 1
r = 0
while l < n:
l *= 2
r += 1
if l == n:
return r
else:
raise ValueError("Not a power of 2")
# cachesize (in 32-bit words) is the size of the data store, must be a power of 2 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
class WB2ASMI: class WB2ASMI:
def __init__(self, cachesize, asmiport): def __init__(self, cachesize, asmiport):
@ -37,9 +26,9 @@ class WB2ASMI:
# Split address: # Split address:
# TAG | LINE NUMBER | LINE OFFSET # TAG | LINE NUMBER | LINE OFFSET
offsetbits = _log2_int(adw//32) offsetbits = log2_int(adw//32)
addressbits = aaw + offsetbits addressbits = aaw + offsetbits
linebits = _log2_int(self.cachesize) - offsetbits linebits = log2_int(self.cachesize) - offsetbits
tagbits = aaw - linebits tagbits = aaw - linebits
adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits) adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)

11
migen/fhdl/structure.py
View file

@ -4,6 +4,17 @@ import re
from migen.fhdl import tracer from migen.fhdl import tracer
def log2_int(n):
l = 1
r = 0
while l < n:
l *= 2
r += 1
if l == n:
return r
else:
raise ValueError("Not a power of 2")
def bits_for(n): def bits_for(n):
if isinstance(n, Constant): if isinstance(n, Constant):
return n.bv.width return n.bv.width