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tools/litex_sim: Update/Fix --with-ethernet.

This commit is contained in:
Florent Kermarrec 2022-06-03 14:52:15 +02:00
parent 3ab7eaa5f7
commit 5c493af573
1 changed files with 1 additions and 1 deletions
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2
litex/tools/litex_sim.py
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@ -248,7 +248,7 @@ class SimSoC(SoCCore):
dw = 64 if ethernet_phy_model == "xgmii" else 32, dw = 64 if ethernet_phy_model == "xgmii" else 32,
interface = "wishbone", interface = "wishbone",
endianness = self.cpu.endianness) endianness = self.cpu.endianness)
ethmac_region_size = (ethmac.rx_slots.read() + ethmac.tx_slots.read()) * ethmac.slot_size.read() ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), ethmac_region_size, type="io") self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), ethmac_region_size, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, ethmac.bus, ethmac_region_size) self.add_wb_slave(self.mem_regions["ethmac"].origin, ethmac.bus, ethmac_region_size)
if self.irq.enabled: if self.irq.enabled: