wishbone: arbiter

This commit is contained in:
Sebastien Bourdeauducq 2011-12-08 23:21:25 +01:00
parent c1041b9a5f
commit 5c7131dc86
1 changed files with 33 additions and 1 deletions

View File

@ -1,5 +1,7 @@
from migen.fhdl import structure as f from migen.fhdl import structure as f
from .simple import Simple from migen.corelogic import roundrobin, multimux
from .simple import Simple, GetSigName
from functools import partial
_desc = [ _desc = [
(True, "adr", 32), (True, "adr", 32),
@ -22,3 +24,33 @@ class Master(Simple):
class Slave(Simple): class Slave(Simple):
def __init__(self, name=""): def __init__(self, name=""):
Simple.__init__(self, _desc, True, name) Simple.__init__(self, _desc, True, name)
class Arbiter:
def __init__(self, masters, target):
self.masters = masters
self.target = target
self.rr = roundrobin.Inst(len(self.masters))
def GetFragment(self):
comb = []
# mux master->slave signals
m2s_names = [GetSigName(x, False) for x in _desc if x[0]]
m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
m2s_target = [getattr(self.target, name) for name in m2s_names]
comb += multimux.MultiMux(self.rr.grant, m2s_masters, m2s_target)
# connect slave->master signals
s2m_names = [GetSigName(x, False) for x in _desc if not x[0]]
for name in s2m_names:
source = getattr(self.target, name)
for m in self.masters:
dest = getattr(m, name)
comb.append(f.Assign(dest, source))
# connect bus requests to round-robin selector
reqs = [m.cyc_o for m in self.masters]
comb.append(f.Assign(self.rr.request, f.Cat(*reqs)))
return f.Fragment(comb) + self.rr.GetFragment()