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CPU: Vex: add debug slave for dbg cpu variant

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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
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Karol Gugala 2021-01-15 09:28:03 +01:00
parent 83fb79fb0c
commit 5d0c5d7088
1 changed files with 5 additions and 0 deletions
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litex/soc/cores/cpu/vexriscv/core.py
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@ -265,6 +265,11 @@ class VexRiscv(CPU, AutoCSR):
vdir = get_data_mod("cpu", "vexriscv").data_location vdir = get_data_mod("cpu", "vexriscv").data_location
platform.add_source(os.path.join(vdir, cpu_filename)) platform.add_source(os.path.join(vdir, cpu_filename))
def add_soc_components(self, soc, soc_region_cls):
if "debug" in self.variant:
soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(origin=0xf00f0000, size=0x100, cached=False))
def use_external_variant(self, variant_filename): def use_external_variant(self, variant_filename):
self.external_variant = True self.external_variant = True
self.platform.add_source(variant_filename) self.platform.add_source(variant_filename)