Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
This commit is contained in:
Sebastien Bourdeauducq
parent
cdd58e023b
commit
5d1dad583b
7
build.py
7
build.py
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@ -4,13 +4,16 @@ import top
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# list Verilog sources before changing directory
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verilog_sources = []
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def add_core_dir(d):
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for root, subFolders, files in os.walk(os.path.join("verilog", d)):
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root = os.path.join("verilog", d)
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files = os.listdir(root)
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for f in files:
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if f[-2:] == ".v":
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verilog_sources.append(os.path.join(root, f))
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def add_core_files(d, files):
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for f in files:
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verilog_sources.append(os.path.join("verilog", d, f))
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add_core_dir("m1crg")
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add_core_dir("s6ddrphy")
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add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
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"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
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"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
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@ -31,7 +34,9 @@ def str2file(filename, contents):
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str2file("soc.v", src_verilog)
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str2file("soc.ucf", src_ucf)
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verilog_sources.append("build/soc.v")
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#raise SystemExit
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# xst
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xst_prj = ""
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for s in verilog_sources:
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@ -1,8 +1,9 @@
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def get(ns, crg0, norflash0, uart0):
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def get(ns, crg0, norflash0, uart0, ddrphy0):
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constraints = []
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def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
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constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
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def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
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assert(signal.bv.width == len(pins))
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i = 0
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for p in pins:
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add(signal, p, i, iostandard, extra)
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@ -12,7 +13,7 @@ def get(ns, crg0, norflash0, uart0):
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add(crg0.ac97_rst_n, "D6")
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add(crg0.videoin_rst_n, "W17")
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add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
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add(crg0.rd_clk_lb, "K5")
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add(crg0.rd_clk_lb, "K5", extra="IOSTANDARD = SSTL2_I")
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add(crg0.trigger_reset, "AA4")
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add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
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@ -29,6 +30,24 @@ def get(ns, crg0, norflash0, uart0):
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add(uart0.tx, "L17", extra="SLEW = SLOW")
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add(uart0.rx, "K18", extra="PULLUP")
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ddrsettings = "IOSTANDARD = SSTL2_I"
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add(ddrphy0.sd_clk_out_p, "M3", extra=ddrsettings)
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add(ddrphy0.sd_clk_out_n, "L4", extra=ddrsettings)
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add_vec(ddrphy0.sd_a, ["B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
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"G6", "C1", "C3", "D1", "D2"], extra=ddrsettings)
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add_vec(ddrphy0.sd_ba, ["A2", "E6"], extra=ddrsettings)
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add(ddrphy0.sd_cs_n, "F7", extra=ddrsettings)
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add(ddrphy0.sd_cke, "G7", extra=ddrsettings)
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add(ddrphy0.sd_ras_n, "E5", extra=ddrsettings)
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add(ddrphy0.sd_cas_n, "C4", extra=ddrsettings)
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add(ddrphy0.sd_we_n, "D3", extra=ddrsettings)
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add_vec(ddrphy0.sd_dq, ["Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
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"U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
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"M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1"],
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extra=ddrsettings)
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add_vec(ddrphy0.sd_dm, ["E1", "E3", "F3", "G4"], extra=ddrsettings)
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add_vec(ddrphy0.sd_dqs, ["F1", "F2", "H5", "H6"], extra=ddrsettings)
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r = ""
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for c in constraints:
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r += "NET \"" + c[0]
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@ -42,6 +61,15 @@ def get(ns, crg0, norflash0, uart0):
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r += """
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TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
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INST "spartan6_soft_phy/datapath_s6_inst/dq_idelay_cal_inst/max_tap_drp" LOC = "IODELAY_X0Y79"; # use sd_dm[0] at E1
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INST "m1crg/wr_bufpll_left" LOC = "BUFPLL_X0Y2";
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INST "m1crg/wr_bufpll_right" LOC = "BUFPLL_X2Y2";
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INST "m1crg/rd_bufpll_left" LOC = "BUFPLL_X0Y3";
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INST "m1crg/rd_bufpll_right" LOC = "BUFPLL_X2Y3";
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# MAP (13.4) hallucinates that this placement is unroutable. Tell it to STFU.
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PIN "m1crg/rd_bufpll_left.IOCLK" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "spartan6_soft_phy/datapath_s6_inst/dq_idelay_cal_inst/max_tap_drp.IOCLK0" CLOCK_DEDICATED_ROUTE = FALSE;
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"""
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return r
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@ -0,0 +1,104 @@
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from migen.fhdl.structure import *
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from migen.bus import dfi
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class S6DDRPHY:
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def __init__(self, a, ba, d):
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ins = []
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outs = []
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inouts = []
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for name in [
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"clk2x_90",
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"clk4x_wr_left",
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"clk4x_wr_strb_left",
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"clk4x_wr_right",
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"clk4x_wr_strb_right",
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"clk4x_rd_left",
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"clk4x_rd_strb_left",
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"clk4x_rd_right",
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"clk4x_rd_strb_right",
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"reset_n"
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]:
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s = Signal(name=name)
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setattr(self, name, s)
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ins.append((name, s))
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self._sd_pins = []
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sd_d = d//4
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for name, width, l in [
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("sd_clk_out_p", 1, outs),
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("sd_clk_out_n", 1, outs),
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("sd_a", a, outs),
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("sd_ba", ba, outs),
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("sd_cs_n", 1, outs),
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("sd_cke", 1, outs),
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("sd_ras_n", 1, outs),
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("sd_cas_n", 1, outs),
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("sd_we_n", 1, outs),
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("sd_dq", sd_d, inouts),
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("sd_dm", sd_d//8, outs),
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("sd_dqs", sd_d//8, inouts)
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]:
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s = Signal(BV(width), name=name)
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setattr(self, name, s)
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l.append((name, s))
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self._sd_pins.append(s)
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self.dfi = dfi.Interface(a, ba, d)
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ins += self.dfi.get_standard_names(True, False)
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outs += self.dfi.get_standard_names(False, True)
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ins += [
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("cfg_al", BV(3)),
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("cfg_cl", BV(3)),
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("cfg_bl", BV(2)),
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("cfg_regdimm", BV(1)),
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("init_done", BV(1)),
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("cpg_busy", BV(1)),
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("diag_dq_recal", BV(1)),
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("diag_io_sel", BV(9)),
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("diag_disable_cal_on_startup", BV(1)),
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("diag_cal_bits", BV(2)),
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("diag_short_cal", BV(1))
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]
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outs += [
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("phy_cal_done", BV(1)),
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("cpg_r_req", BV(1)),
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("cpg_w_req", BV(1)),
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("cpg_addr", BV(a)),
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("cpg_b_size", BV(4))
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]
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self._inst = Instance("spartan6_soft_phy",
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outs,
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ins,
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inouts,
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[
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("DSIZE", d),
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("NUM_AD", a),
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("NUM_BA", ba),
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("ADDR_WIDTH", 31),
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("DQ_IO_LOC", Constant(2**32-1, BV(32))),
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("DM_IO_LOC", Constant(2**4-1, BV(4)))
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],
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clkport="clk")
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def get_fragment(self):
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comb = [
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self._inst.ins["cfg_al"].eq(0),
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self._inst.ins["cfg_cl"].eq(3),
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self._inst.ins["cfg_bl"].eq(1),
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self._inst.ins["cfg_regdimm"].eq(0),
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self._inst.ins["diag_dq_recal"].eq(0),
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self._inst.ins["diag_io_sel"].eq(0),
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self._inst.ins["diag_disable_cal_on_startup"].eq(0),
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self._inst.ins["diag_cal_bits"].eq(0),
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self._inst.ins["diag_short_cal"].eq(0)
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]
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return Fragment(comb, instances=[self._inst], pads=set(self._sd_pins))
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23
top.py
23
top.py
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@ -4,7 +4,7 @@ from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr
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from milkymist import m1crg, lm32, norflash, uart, sram#, s6ddrphy
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from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy
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import constraints
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MHz = 1000000
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@ -12,11 +12,26 @@ clk_freq = (83 + Fraction(1, 3))*MHz
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sram_size = 4096 # in bytes
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l2_size = 8192 # in bytes
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def ddrphy_clocking(crg, phy):
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names = [
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"clk2x_90",
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"clk4x_wr_left",
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"clk4x_wr_strb_left",
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"clk4x_wr_right",
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"clk4x_wr_strb_right",
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"clk4x_rd_left",
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"clk4x_rd_strb_left",
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"clk4x_rd_right",
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"clk4x_rd_strb_right",
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]
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comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
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return Fragment(comb)
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def get():
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#
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# ASMI
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#
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#ddrphy0 = s6ddrphy.S6DDRPHY(13, 2, 128)
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ddrphy0 = s6ddrphy.S6DDRPHY(13, 2, 128)
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asmihub0 = asmibus.Hub(23, 128, 12) # TODO: get hub from memory controller
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asmiport_wb = asmihub0.get_port()
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asmihub0.finalize()
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@ -67,12 +82,12 @@ def get():
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#
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crg0 = m1crg.M1CRG(50*MHz, clk_freq)
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frag = autofragment.from_local() + interrupts
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frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
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src_verilog, vns = verilog.convert(frag,
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{crg0.trigger_reset},
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name="soc",
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clk_signal=crg0.sys_clk,
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rst_signal=crg0.sys_rst,
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return_ns=True)
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src_ucf = constraints.get(vns, crg0, norflash0, uart0)
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src_ucf = constraints.get(vns, crg0, norflash0, uart0, ddrphy0)
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return (src_verilog, src_ucf)
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