Merge branch 'master' into master
This commit is contained in:
enjoy-digital
GitHub
commit
5d895bd3a7
|
|
@ -9,6 +9,9 @@
|
|||
- litespi/software: : Fixed SPI Flash Clk Divider computation when with L2 Cache.
|
||||
- litepcie/us(p)pciephy : Fixed x8 / 256-bit wide case.
|
||||
- litex_sim/serial2console : Fixed RX backpressure handling.
|
||||
- litedram/frontend/avalon : Fixed and cleaned-up.
|
||||
- litex_sim/video : Fixed pixel format to RGBA.
|
||||
- build/xilinx/common : Fixed missing clk parameter on XilinxSDRTristateImpl.
|
||||
|
||||
[> Added
|
||||
--------
|
||||
|
|
@ -27,6 +30,11 @@
|
|||
- litex_sim : Added jtagremote support.
|
||||
- soc/add_master : Added region support to allow/limit access to a specific region.
|
||||
- litex_json2dts_linux : Added ip= bootarg when local/remote ips are defined.
|
||||
- cores/jtag : Added JTAGBone support for Zynq.
|
||||
- cores/ram/lattice_nx : Improved timings.
|
||||
- liteeth_gen : Added QPLL/BUFH/BUFG parameters for A7 1000BaseX PHY.
|
||||
- litex_sim : Added Video Color Bar support.
|
||||
- cpu/neorv32 : Updated to v1.9.7.
|
||||
|
||||
[> Changed
|
||||
----------
|
||||
|
|
|
|||
|
|
@ -125,26 +125,24 @@ class EfinixPlatform(GenericPlatform):
|
|||
sig = sig.value
|
||||
return sig
|
||||
|
||||
def get_pin_name(self, sig, without_index=False):
|
||||
def get_pin_name(self, sig):
|
||||
if sig is None:
|
||||
return None
|
||||
assert len(sig) == 1
|
||||
idx = 0
|
||||
slc = False
|
||||
while isinstance(sig, _Slice) and hasattr(sig, "value"):
|
||||
slc = True
|
||||
idx = sig.start
|
||||
sig = sig.value
|
||||
slc = hasattr(sig, "nbits") and sig.nbits > 1
|
||||
sc = self.constraint_manager.get_sig_constraints()
|
||||
for s, pins, others, resource in sc:
|
||||
if s == sig:
|
||||
name = resource[0] + (f"{resource[1]}" if resource[1] is not None else "")
|
||||
if resource[2]:
|
||||
name = resource[0] + "_" + resource[2]
|
||||
if without_index is False:
|
||||
name = name + (f"{idx}" if slc else "")
|
||||
return name
|
||||
else:
|
||||
return resource[0] + (f"{idx}" if slc else "")
|
||||
name = name + "_" + resource[2]
|
||||
name = name + (f"{idx}" if slc else "")
|
||||
return name
|
||||
return None
|
||||
|
||||
def get_pad_name(self, sig):
|
||||
|
|
|
|||
|
|
@ -40,6 +40,12 @@ class OpenOCD(GenericProgrammer):
|
|||
])
|
||||
self.call(["openocd", "-f", config, "-c", script])
|
||||
|
||||
def get_tap_name(self, config):
|
||||
cfg_str = open(config).read()
|
||||
if "zynq_7000" in cfg_str:
|
||||
return "zynq_pl.bs"
|
||||
return "$_CHIPNAME.tap"
|
||||
|
||||
def get_ir(self, chain, config):
|
||||
cfg_str = open(config).read()
|
||||
# Lattice ECP5.
|
||||
|
|
@ -98,6 +104,7 @@ class OpenOCD(GenericProgrammer):
|
|||
- TX valid : bit 9
|
||||
"""
|
||||
config = self.find_config()
|
||||
tap_name = self.get_tap_name(config)
|
||||
ir = self.get_ir(chain, config)
|
||||
endstate = self.get_endstate(config)
|
||||
cfg = """
|
||||
|
|
@ -185,8 +192,9 @@ proc jtagstream_serve {tap port} {
|
|||
write_to_file("stream.cfg", cfg)
|
||||
script = "; ".join([
|
||||
"init",
|
||||
"irscan $_CHIPNAME.tap {:d}".format(ir),
|
||||
"jtagstream_serve $_CHIPNAME.tap {:d}".format(port),
|
||||
#"poll off", # FIXME: not supported for ECP5
|
||||
"irscan {} {:d}".format(tap_name, ir),
|
||||
"jtagstream_serve {} {:d}".format(tap_name, port),
|
||||
"exit",
|
||||
])
|
||||
self.call(["openocd", "-f", config, "-f", "stream.cfg", "-c", script])
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ bool fb_init(unsigned width, unsigned height, bool vsync, fb_handle_t *handle)
|
|||
if (!handle->renderer)
|
||||
return false;
|
||||
|
||||
handle->texture = SDL_CreateTexture(handle->renderer, SDL_PIXELFORMAT_BGRA32, SDL_TEXTUREACCESS_TARGET, width, height);
|
||||
handle->texture = SDL_CreateTexture(handle->renderer, SDL_PIXELFORMAT_RGBA32, SDL_TEXTUREACCESS_TARGET, width, height);
|
||||
if (!handle->texture)
|
||||
return false;
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <json-c/json.h>
|
||||
#include "error.h"
|
||||
#include <unistd.h>
|
||||
#include <event2/listener.h>
|
||||
|
|
@ -29,6 +30,7 @@ struct session_s {
|
|||
unsigned frame, stride;
|
||||
uint8_t *buf, *pbuf;
|
||||
fb_handle_t fb;
|
||||
char render_on_vsync;
|
||||
};
|
||||
|
||||
static int litex_sim_module_pads_get(struct pad_s *pads, char *name, void **signal)
|
||||
|
|
@ -56,6 +58,30 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int videosim_parse_args(struct session_s *s, const char *args)
|
||||
{
|
||||
int ret = RC_OK;
|
||||
json_object *args_json = NULL;
|
||||
json_object *render_on_vsync_json = NULL;
|
||||
|
||||
args_json = json_tokener_parse(args);
|
||||
if (!args_json) {
|
||||
ret = RC_JSERROR;
|
||||
fprintf(stderr, "[video] Could not parse args: %s\n", args);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if(json_object_object_get_ex(args_json, "render_on_vsync", &render_on_vsync_json)) {
|
||||
s->render_on_vsync = json_object_get_boolean(render_on_vsync_json);
|
||||
} else {
|
||||
s->render_on_vsync = false;
|
||||
}
|
||||
|
||||
out:
|
||||
if(args_json) json_object_put(args_json);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int videosim_start(void *b)
|
||||
{
|
||||
printf("[video] loaded (%p)\n", (struct event_base *)b);
|
||||
|
|
@ -79,6 +105,7 @@ static int videosim_new(void **sess, char *args)
|
|||
}
|
||||
memset(s, 0, sizeof(struct session_s));
|
||||
|
||||
if (args) videosim_parse_args(s, args);
|
||||
out:
|
||||
*sess = (void*) s;
|
||||
return ret;
|
||||
|
|
@ -143,6 +170,14 @@ static int videosim_tick(void *sess, uint64_t time_ps) {
|
|||
fb_init(s->hres, s->vres, false, &s->fb);
|
||||
s->stride = s->hres*sizeof(uint32_t);
|
||||
}
|
||||
if (s->render_on_vsync) {
|
||||
if(fb_should_quit())
|
||||
{
|
||||
fb_deinit(&s->fb);
|
||||
exit(1); //FIXME: end gracefully
|
||||
}
|
||||
fb_update(&s->fb, s->buf, s->stride);
|
||||
}
|
||||
s->y = 0;
|
||||
s->pbuf = s->buf;
|
||||
++s->frame;
|
||||
|
|
@ -164,12 +199,14 @@ static int videosim_tick(void *sess, uint64_t time_ps) {
|
|||
{
|
||||
if(s->buf) //update each horizontal line
|
||||
{
|
||||
if(fb_should_quit())
|
||||
{
|
||||
fb_deinit(&s->fb);
|
||||
exit(1); //FIXME: end gracefully
|
||||
if (!s->render_on_vsync) {
|
||||
if(fb_should_quit())
|
||||
{
|
||||
fb_deinit(&s->fb);
|
||||
exit(1); //FIXME: end gracefully
|
||||
}
|
||||
fb_update(&s->fb, s->buf, s->stride);
|
||||
}
|
||||
fb_update(&s->fb, s->buf, s->stride);
|
||||
s->pbuf = s->buf + s->y*s->stride;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -141,9 +141,9 @@ class XilinxSDRTristateImpl(Module):
|
|||
_o = Signal()
|
||||
_oe_n = Signal()
|
||||
_i = Signal()
|
||||
self.specials += SDROutput(o, _o)
|
||||
self.specials += SDROutput(~oe, _oe_n)
|
||||
self.specials += SDRInput(_i, i)
|
||||
self.specials += SDROutput(o, _o, clk)
|
||||
self.specials += SDROutput(~oe, _oe_n, clk)
|
||||
self.specials += SDRInput(_i, i, clk)
|
||||
self.specials += Instance("IOBUF",
|
||||
io_IO = io,
|
||||
o_O = _i,
|
||||
|
|
|
|||
|
|
@ -171,11 +171,14 @@ class NEORV32(CPU):
|
|||
"neorv32_application_image.vhd",
|
||||
"neorv32_bootloader_image.vhd",
|
||||
"neorv32_boot_rom.vhd",
|
||||
"neorv32_cache.vhd",
|
||||
"neorv32_cfs.vhd",
|
||||
"neorv32_clockgate.vhd",
|
||||
"neorv32_cpu_alu.vhd",
|
||||
"neorv32_cpu_control.vhd",
|
||||
"neorv32_cpu_cp_bitmanip.vhd",
|
||||
"neorv32_cpu_cp_cfu.vhd",
|
||||
"neorv32_cpu_cp_cond.vhd",
|
||||
"neorv32_cpu_cp_fpu.vhd",
|
||||
"neorv32_cpu_cp_muldiv.vhd",
|
||||
"neorv32_cpu_cp_shifter.vhd",
|
||||
|
|
@ -185,7 +188,6 @@ class NEORV32(CPU):
|
|||
"neorv32_cpu_regfile.vhd",
|
||||
"neorv32_cpu.vhd",
|
||||
"neorv32_crc.vhd",
|
||||
"neorv32_dcache.vhd",
|
||||
"neorv32_debug_dm.vhd",
|
||||
"neorv32_debug_dtm.vhd",
|
||||
"neorv32_dma.vhd",
|
||||
|
|
@ -193,7 +195,6 @@ class NEORV32(CPU):
|
|||
"neorv32_fifo.vhd",
|
||||
"neorv32_gpio.vhd",
|
||||
"neorv32_gptmr.vhd",
|
||||
"neorv32_icache.vhd",
|
||||
"neorv32_imem.entity.vhd",
|
||||
"neorv32_intercon.vhd",
|
||||
"neorv32_mtime.vhd",
|
||||
|
|
@ -210,7 +211,7 @@ class NEORV32(CPU):
|
|||
"neorv32_twi.vhd",
|
||||
"neorv32_uart.vhd",
|
||||
"neorv32_wdt.vhd",
|
||||
"neorv32_wishbone.vhd",
|
||||
"neorv32_xbus.vhd",
|
||||
"neorv32_xip.vhd",
|
||||
"neorv32_xirq.vhd",
|
||||
],
|
||||
|
|
@ -226,8 +227,8 @@ class NEORV32(CPU):
|
|||
}
|
||||
|
||||
# Download VHDL sources (if not already present).
|
||||
# Version 1.8.9
|
||||
sha1 = "fdb00a5d24e256ac9a9cb29410f2653c95068c91"
|
||||
# Version 1.9.7
|
||||
sha1 = "ed17ae4df64e6a5221562e4adf4de378eaf0c2e8"
|
||||
for directory, vhds in sources.items():
|
||||
for vhd in vhds:
|
||||
self.vhd2v_converter.add_source(os.path.join(cdir, vhd))
|
||||
|
|
|
|||
|
|
@ -79,10 +79,10 @@ class NXLRAM(LiteXModule):
|
|||
wren = Signal()
|
||||
self.comb += [
|
||||
datain.eq(self.bus.dat_w[32*w:32*(w+1)]),
|
||||
self.bus.dat_r[32*w:32*(w+1)].eq(dataout),
|
||||
If(self.bus.adr[14:14+self.depth_cascading.bit_length()] == d,
|
||||
cs.eq(1),
|
||||
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
|
||||
self.bus.dat_r[32*w:32*(w+1)].eq(dataout)
|
||||
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc)
|
||||
),
|
||||
]
|
||||
lram_block = Instance("SP512K",
|
||||
|
|
|
|||
|
|
@ -92,7 +92,9 @@ class Builder:
|
|||
# Documentation.
|
||||
generate_doc = False):
|
||||
|
||||
self.soc = soc
|
||||
# SoC/Builder Attach.
|
||||
self.soc = soc # Attach SoC to Builder.
|
||||
self.soc.builder = self # Attach Builder to SoC.
|
||||
|
||||
# Directories.
|
||||
self.output_dir = os.path.abspath(output_dir or os.path.join("build", soc.platform.name))
|
||||
|
|
@ -331,7 +333,7 @@ class Builder:
|
|||
)
|
||||
|
||||
# Initialize SoC with with BIOS data.
|
||||
self.soc.initialize_rom(bios_data)
|
||||
self.soc.init_rom(name="rom", contents=bios_data)
|
||||
|
||||
def build(self, **kwargs):
|
||||
# Pass Output Directory to Platform.
|
||||
|
|
@ -388,9 +390,16 @@ class Builder:
|
|||
self._prepare_rom_software()
|
||||
self._generate_rom_software(compile_bios=use_bios)
|
||||
|
||||
# Initialize Memories.
|
||||
# Allow User Design to optionally initialize Memories through SoC.init_ram/init_rom.
|
||||
if hasattr(self.soc, "init_mems"):
|
||||
self.soc.init_mems(**kwargs)
|
||||
|
||||
# Initialize ROM.
|
||||
if use_bios and self.soc.integrated_rom_size:
|
||||
self._initialize_rom_software()
|
||||
# Only initialize if not already initialized.
|
||||
if not getattr(self.soc, "rom").mem.init:
|
||||
self._initialize_rom_software()
|
||||
|
||||
# Translate compile_gateware to run.
|
||||
if "run" not in kwargs:
|
||||
|
|
|
|||
|
|
@ -265,9 +265,10 @@ def get_csr_header(regions, constants, csr_base=None, with_csr_base_define=True,
|
|||
r += f"#define CSR_BASE {hex(csr_base)}L\n"
|
||||
r += "#endif\n"
|
||||
for name, region in regions.items():
|
||||
origin = region.origin - _csr_base
|
||||
origin = region.origin - _csr_base
|
||||
base_define = not isinstance(region, MockCSRRegion)
|
||||
r += "\n/* "+name+" */\n"
|
||||
r += f"#define CSR_{name.upper()}_BASE {_get_csr_addr(csr_base, origin, with_csr_base_define)}\n"
|
||||
r += f"#define CSR_{name.upper()}_BASE {_get_csr_addr(csr_base, origin, base_define)}\n"
|
||||
if not isinstance(region.obj, Memory):
|
||||
for csr in region.obj:
|
||||
nr = (csr.size + region.busword - 1)//region.busword
|
||||
|
|
@ -279,7 +280,7 @@ def get_csr_header(regions, constants, csr_base=None, with_csr_base_define=True,
|
|||
alignment = alignment,
|
||||
read_only = getattr(csr, "read_only", False),
|
||||
csr_base = csr_base,
|
||||
with_csr_base_define = with_csr_base_define,
|
||||
with_csr_base_define = base_define,
|
||||
with_access_functions = with_access_functions,
|
||||
)
|
||||
origin += alignment//8*nr
|
||||
|
|
|
|||
|
|
@ -1027,6 +1027,8 @@ class SoC(LiteXModule, SoCCoreCompat):
|
|||
raise SoCError()
|
||||
|
||||
# SoC Main Components --------------------------------------------------------------------------
|
||||
|
||||
# Add Controller -------------------------------------------------------------------------------
|
||||
def add_controller(self, name="ctrl", **kwargs):
|
||||
self.check_if_exists(name)
|
||||
self.logger.info("Controller {} {}.".format(
|
||||
|
|
@ -1034,6 +1036,7 @@ class SoC(LiteXModule, SoCCoreCompat):
|
|||
colorer("added", color="green")))
|
||||
self.add_module(name=name, module=SoCController(**kwargs))
|
||||
|
||||
# Add/Init RAM ---------------------------------------------------------------------------------
|
||||
def add_ram(self, name, origin, size, contents=[], mode="rwx"):
|
||||
ram_cls = {
|
||||
"wishbone": wishbone.SRAM,
|
||||
|
|
@ -1050,7 +1053,7 @@ class SoC(LiteXModule, SoCCoreCompat):
|
|||
address_width = self.bus.address_width,
|
||||
bursting = self.bus.bursting
|
||||
)
|
||||
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=("w" not in mode), name=name)
|
||||
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=("w" not in mode), name=name)
|
||||
self.bus.add_slave(name=name, slave=ram.bus, region=SoCRegion(origin=origin, size=size, mode=mode))
|
||||
self.check_if_exists(name)
|
||||
self.logger.info("RAM {} {} {}.".format(
|
||||
|
|
@ -1061,21 +1064,50 @@ class SoC(LiteXModule, SoCCoreCompat):
|
|||
if contents != []:
|
||||
self.add_config(f"{name}_INIT", 1)
|
||||
|
||||
def init_ram(self, name, contents=[], auto_size=False):
|
||||
# RAM Parameters.
|
||||
ram = getattr(self, name)
|
||||
ram_region = self.bus.regions[name]
|
||||
ram_type = {
|
||||
True : "ROM",
|
||||
False : "RAM",
|
||||
}["w" not in ram_region.mode]
|
||||
contents_size = 4*len(contents) # FIXME.
|
||||
|
||||
# Size Check.
|
||||
if ram_region.size < contents_size:
|
||||
self.logger.error("Contents Size ({}) {} {} Size ({}).".format(
|
||||
colorer(f"0x{contents_size:x}"),
|
||||
colorer("exceeds", color="red"),
|
||||
ram_type,
|
||||
colorer(f"0x{ram_region.size:x}"),
|
||||
))
|
||||
raise SoCError()
|
||||
|
||||
# RAM Initialization.
|
||||
self.logger.info("Initializing {} {} with contents (Size: {}).".format(
|
||||
ram_type,
|
||||
colorer(name),
|
||||
colorer(f"0x{contents_size:x}")))
|
||||
ram.mem.init = contents
|
||||
|
||||
# RAM Auto-Resize (Optional).
|
||||
if auto_size and ("w" not in ram_region.mode):
|
||||
self.logger.info("Auto-Resizing {} {} from {} to {}.".format(
|
||||
ram_type,
|
||||
colorer(name),
|
||||
colorer(f"0x{ram_region.size:x}"),
|
||||
colorer(f"0x{contents_size:x}")))
|
||||
ram.mem.depth = len(contents)
|
||||
|
||||
# Add/Init ROM ---------------------------------------------------------------------------------
|
||||
def add_rom(self, name, origin, size, contents=[], mode="rx"):
|
||||
self.add_ram(name, origin, size, contents, mode=mode)
|
||||
|
||||
def init_rom(self, name, contents=[], auto_size=True):
|
||||
self.logger.info("Initializing ROM {} with contents (Size: {}).".format(
|
||||
colorer(name),
|
||||
colorer(f"0x{4*len(contents):x}")))
|
||||
getattr(self, name).mem.init = contents
|
||||
if auto_size and "w" not in self.bus.regions[name].mode:
|
||||
self.logger.info("Auto-Resizing ROM {} from {} to {}.".format(
|
||||
colorer(name),
|
||||
colorer(f"0x{self.bus.regions[name].size:x}"),
|
||||
colorer(f"0x{4*len(contents):x}")))
|
||||
getattr(self, name).mem.depth = len(contents)
|
||||
self.init_ram(name, contents, auto_size)
|
||||
|
||||
# Add CSR Bridge -------------------------------------------------------------------------------
|
||||
def add_csr_bridge(self, name="csr", origin=None, register=False):
|
||||
csr_bridge_cls = {
|
||||
"wishbone": wishbone.Wishbone2CSR,
|
||||
|
|
@ -1114,6 +1146,7 @@ class SoC(LiteXModule, SoCCoreCompat):
|
|||
self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
|
||||
self.add_config("CSR_ALIGNMENT", self.csr.alignment)
|
||||
|
||||
# Add CPU --------------------------------------------------------------------------------------
|
||||
def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=None):
|
||||
from litex.soc.cores import cpu
|
||||
|
||||
|
|
@ -1257,6 +1290,7 @@ class SoC(LiteXModule, SoCCoreCompat):
|
|||
if hasattr(self.cpu, "nop"):
|
||||
self.add_config("CPU_NOP", self.cpu.nop)
|
||||
|
||||
# Add Timer ------------------------------------------------------------------------------------
|
||||
def add_timer(self, name="timer0"):
|
||||
from litex.soc.cores.timer import Timer
|
||||
self.check_if_exists(name)
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ __all__ = [
|
|||
# SoCCore ------------------------------------------------------------------------------------------
|
||||
|
||||
class SoCCore(LiteXSoC):
|
||||
# Default register/interrupt/memory mappings (can be redefined by user)
|
||||
# Default register/interrupt/memory mappings (can be redefined by user).
|
||||
csr_map = {}
|
||||
interrupt_map = {}
|
||||
mem_map = {
|
||||
|
|
@ -52,7 +52,7 @@ class SoCCore(LiteXSoC):
|
|||
}
|
||||
|
||||
def __init__(self, platform, clk_freq,
|
||||
# Bus parameters
|
||||
# Bus parameters.
|
||||
bus_standard = "wishbone",
|
||||
bus_data_width = 32,
|
||||
bus_address_width = 32,
|
||||
|
|
@ -60,62 +60,62 @@ class SoCCore(LiteXSoC):
|
|||
bus_bursting = False,
|
||||
bus_interconnect = "shared",
|
||||
|
||||
# CPU parameters
|
||||
# CPU parameters.
|
||||
cpu_type = "vexriscv",
|
||||
cpu_reset_address = None,
|
||||
cpu_variant = None,
|
||||
cpu_cfu = None,
|
||||
|
||||
# CFU parameters
|
||||
# CFU parameters.
|
||||
cfu_filename = None,
|
||||
|
||||
# ROM parameters
|
||||
# ROM parameters.
|
||||
integrated_rom_size = 0,
|
||||
integrated_rom_mode = "rx",
|
||||
integrated_rom_init = [],
|
||||
|
||||
# SRAM parameters
|
||||
# SRAM parameters.
|
||||
integrated_sram_size = 0x2000,
|
||||
integrated_sram_init = [],
|
||||
|
||||
# MAIN_RAM parameters
|
||||
# MAIN_RAM parameters.
|
||||
integrated_main_ram_size = 0,
|
||||
integrated_main_ram_init = [],
|
||||
|
||||
# CSR parameters
|
||||
# CSR parameters.
|
||||
csr_data_width = 32,
|
||||
csr_address_width = 14,
|
||||
csr_paging = 0x800,
|
||||
csr_ordering = "big",
|
||||
|
||||
# Interrupt parameters
|
||||
# Interrupt parameters.
|
||||
irq_n_irqs = 32,
|
||||
|
||||
# Identifier parameters
|
||||
# Identifier parameters.
|
||||
ident = "",
|
||||
ident_version = False,
|
||||
|
||||
# UART parameters
|
||||
# UART parameters.
|
||||
with_uart = True,
|
||||
uart_name = "serial",
|
||||
uart_baudrate = 115200,
|
||||
uart_fifo_depth = 16,
|
||||
|
||||
# Timer parameters
|
||||
# Timer parameters.
|
||||
with_timer = True,
|
||||
timer_uptime = False,
|
||||
|
||||
# Controller parameters
|
||||
# Controller parameters.
|
||||
with_ctrl = True,
|
||||
|
||||
# JTAGBone
|
||||
# JTAGBone.
|
||||
with_jtagbone = False,
|
||||
jtagbone_chain = 1,
|
||||
|
||||
# UARTBone
|
||||
# UARTBone.
|
||||
with_uartbone = False,
|
||||
|
||||
# Others
|
||||
# Others.
|
||||
**kwargs):
|
||||
|
||||
# New LiteXSoC class -----------------------------------------------------------------------
|
||||
|
|
@ -138,7 +138,7 @@ class SoCCore(LiteXSoC):
|
|||
irq_reserved_irqs = {},
|
||||
)
|
||||
|
||||
# Attributes
|
||||
# Attributes.
|
||||
self.mem_regions = self.bus.regions
|
||||
self.clk_freq = self.sys_clk_freq
|
||||
self.mem_map = self.mem_map
|
||||
|
|
@ -198,28 +198,29 @@ class SoCCore(LiteXSoC):
|
|||
|
||||
# JTAGBone and jtag_uart can't be used at the same time.
|
||||
assert not (with_jtagbone and uart_name == "jtag_uart")
|
||||
|
||||
# UARTBone and serial can't be used at the same time.
|
||||
assert not (with_uartbone and uart_name == "serial")
|
||||
|
||||
# Modules instances ------------------------------------------------------------------------
|
||||
|
||||
# Add SoCController
|
||||
# Add SoCController.
|
||||
if with_ctrl:
|
||||
self.add_controller("ctrl")
|
||||
|
||||
# Add CPU
|
||||
# Add CPU.
|
||||
self.add_cpu(
|
||||
name = str(cpu_type),
|
||||
variant = "standard" if cpu_variant is None else cpu_variant,
|
||||
reset_address = None if integrated_rom_size else cpu_reset_address,
|
||||
cfu = cpu_cfu)
|
||||
|
||||
# Add User's interrupts
|
||||
# Add User's interrupts.
|
||||
if self.irq.enabled:
|
||||
for name, loc in self.interrupt_map.items():
|
||||
self.irq.add(name, loc)
|
||||
|
||||
# Add integrated ROM
|
||||
# Add integrated ROM.
|
||||
if integrated_rom_size:
|
||||
self.add_rom("rom",
|
||||
origin = self.cpu.reset_address,
|
||||
|
|
@ -228,14 +229,14 @@ class SoCCore(LiteXSoC):
|
|||
mode = integrated_rom_mode
|
||||
)
|
||||
|
||||
# Add integrated SRAM
|
||||
# Add integrated SRAM.
|
||||
if integrated_sram_size:
|
||||
self.add_ram("sram",
|
||||
origin = self.mem_map["sram"],
|
||||
size = integrated_sram_size,
|
||||
)
|
||||
|
||||
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
|
||||
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available).
|
||||
if integrated_main_ram_size:
|
||||
self.add_ram("main_ram",
|
||||
origin = self.mem_map["main_ram"],
|
||||
|
|
@ -243,23 +244,23 @@ class SoCCore(LiteXSoC):
|
|||
contents = integrated_main_ram_init,
|
||||
)
|
||||
|
||||
# Add Identifier
|
||||
# Add Identifier.
|
||||
if ident != "":
|
||||
self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
|
||||
|
||||
# Add UARTBone
|
||||
# Add UARTBone.
|
||||
if with_uartbone:
|
||||
self.add_uartbone(baudrate=uart_baudrate)
|
||||
|
||||
# Add UART
|
||||
# Add UART.
|
||||
if with_uart:
|
||||
self.add_uart(name="uart", uart_name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth)
|
||||
|
||||
# Add JTAGBone
|
||||
# Add JTAGBone.
|
||||
if with_jtagbone:
|
||||
self.add_jtagbone(chain=jtagbone_chain)
|
||||
|
||||
# Add Timer
|
||||
# Add Timer.
|
||||
if with_timer:
|
||||
self.add_timer(name="timer0")
|
||||
if timer_uptime:
|
||||
|
|
@ -270,9 +271,6 @@ class SoCCore(LiteXSoC):
|
|||
def add_csr(self, csr_name, csr_id=None, use_loc_if_exists=False):
|
||||
self.csr.add(csr_name, csr_id, use_loc_if_exists=use_loc_if_exists)
|
||||
|
||||
def initialize_rom(self, data):
|
||||
self.init_rom(name="rom", contents=data)
|
||||
|
||||
def add_memory_region(self, name, origin, length, type="cached"):
|
||||
self.bus.add_region(name, SoCRegion(origin=origin, size=length,
|
||||
cached="cached" in type,
|
||||
|
|
@ -286,7 +284,7 @@ class SoCCore(LiteXSoC):
|
|||
|
||||
def soc_core_args(parser):
|
||||
soc_group = parser.add_argument_group(title="SoC options")
|
||||
# Bus parameters
|
||||
# Bus parameters.
|
||||
soc_group.add_argument("--bus-standard", default="wishbone", help="Select bus standard: {}.".format(", ".join(SoCBusHandler.supported_standard)))
|
||||
soc_group.add_argument("--bus-data-width", default=32, type=auto_int, help="Bus data-width.")
|
||||
soc_group.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width.")
|
||||
|
|
@ -294,53 +292,53 @@ def soc_core_args(parser):
|
|||
soc_group.add_argument("--bus-bursting", action="store_true", help="Enable burst cycles on the bus if supported.")
|
||||
soc_group.add_argument("--bus-interconnect", default="shared", help="Select bus interconnect: shared (default) or crossbar.")
|
||||
|
||||
# CPU parameters
|
||||
# CPU parameters.
|
||||
soc_group.add_argument("--cpu-type", default="vexriscv", help="Select CPU: {}.".format(", ".join(iter(cpu.CPUS.keys()))))
|
||||
soc_group.add_argument("--cpu-variant", default=None, help="CPU variant.")
|
||||
soc_group.add_argument("--cpu-reset-address", default=None, type=auto_int, help="CPU reset address (Boot from Integrated ROM by default).")
|
||||
soc_group.add_argument("--cpu-cfu", default=None, help="Optional CPU CFU file/instance to add to the CPU.")
|
||||
|
||||
# Controller parameters
|
||||
# Controller parameters.
|
||||
soc_group.add_argument("--no-ctrl", action="store_true", help="Disable Controller.")
|
||||
|
||||
# ROM parameters
|
||||
# ROM parameters.
|
||||
soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).")
|
||||
soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).")
|
||||
|
||||
# SRAM parameters
|
||||
# SRAM parameters.
|
||||
soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.")
|
||||
|
||||
# MAIN_RAM parameters
|
||||
# MAIN_RAM parameters.
|
||||
soc_group.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM.")
|
||||
|
||||
# CSR parameters
|
||||
# CSR parameters.
|
||||
soc_group.add_argument("--csr-data-width", default=32 , type=auto_int, help="CSR bus data-width (8 or 32).")
|
||||
soc_group.add_argument("--csr-address-width", default=14, type=auto_int, help="CSR bus address-width.")
|
||||
soc_group.add_argument("--csr-paging", default=0x800, type=auto_int, help="CSR bus paging.")
|
||||
soc_group.add_argument("--csr-ordering", default="big", help="CSR registers ordering (big or little).")
|
||||
|
||||
# Identifier parameters
|
||||
# Identifier parameters.
|
||||
soc_group.add_argument("--ident", default=None, type=str, help="SoC identifier.")
|
||||
soc_group.add_argument("--no-ident-version", action="store_true", help="Disable date/time in SoC identifier.")
|
||||
|
||||
# UART parameters
|
||||
# UART parameters.
|
||||
soc_group.add_argument("--no-uart", action="store_true", help="Disable UART.")
|
||||
soc_group.add_argument("--uart-name", default="serial", type=str, help="UART type/name.")
|
||||
soc_group.add_argument("--uart-baudrate", default=115200, type=auto_int, help="UART baudrate.")
|
||||
soc_group.add_argument("--uart-fifo-depth", default=16, type=auto_int, help="UART FIFO depth.")
|
||||
|
||||
# UARTBone parameters
|
||||
# UARTBone parameters.
|
||||
soc_group.add_argument("--with-uartbone", action="store_true", help="Enable UARTbone.")
|
||||
|
||||
# JTAGBone parameters
|
||||
# JTAGBone parameters.
|
||||
soc_group.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
|
||||
soc_group.add_argument("--jtagbone-chain", default=1, type=int, help="Jtagbone chain index.")
|
||||
|
||||
# Timer parameters
|
||||
# Timer parameters.
|
||||
soc_group.add_argument("--no-timer", action="store_true", help="Disable Timer.")
|
||||
soc_group.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer.")
|
||||
|
||||
# L2 Cache
|
||||
# L2 Cache.
|
||||
soc_group.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size.")
|
||||
|
||||
def soc_core_argdict(args):
|
||||
|
|
@ -366,7 +364,7 @@ def soc_core_argdict(args):
|
|||
r[a] = arg
|
||||
return r
|
||||
|
||||
# SoCMini ---------------------------------------------------------------------------------------
|
||||
# SoCMini ------------------------------------------------------------------------------------------
|
||||
|
||||
class SoCMini(SoCCore):
|
||||
def __init__(self, *args, **kwargs):
|
||||
|
|
@ -381,7 +379,7 @@ class SoCMini(SoCCore):
|
|||
|
||||
SoCCore.__init__(self, *args, **kwargs)
|
||||
|
||||
# SoCMini arguments -----------------------------------------------------------------------------
|
||||
# SoCMini arguments --------------------------------------------------------------------------------
|
||||
|
||||
soc_mini_args = soc_core_args
|
||||
soc_mini_argdict = soc_core_argdict
|
||||
|
|
|
|||
|
|
@ -254,8 +254,16 @@ class ClockDomainCrossing(LiteXModule, DUID):
|
|||
|
||||
# Same Clk Domains.
|
||||
if cd_from == cd_to:
|
||||
# No adaptation.
|
||||
self.comb += self.sink.connect(self.source)
|
||||
if buffered:
|
||||
# Add Buffer.
|
||||
self.buffer = ClockDomainsRenamer(cd_from)(Buffer(layout))
|
||||
self.comb += [
|
||||
self.sink.connect(self.buffer.sink),
|
||||
self.buffer.source.connect(self.source),
|
||||
]
|
||||
else:
|
||||
# No adaptation.
|
||||
self.comb += self.sink.connect(self.source)
|
||||
# Different Clk Domains.
|
||||
else:
|
||||
if with_common_rst:
|
||||
|
|
|
|||
|
|
@ -32,7 +32,26 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
|
|||
ncpus = int(d["constants"].get("config_cpu_count", 1))
|
||||
cpu_name = d["constants"].get("config_cpu_name")
|
||||
cpu_arch = cpu_architectures[cpu_name]
|
||||
cpu_isa = d["constants"].get("config_cpu_isa", None)
|
||||
cpu_isa = d["constants"].get("config_cpu_isa", None) # kernel < 6.6.0
|
||||
|
||||
# kernel >= 6.6.0
|
||||
cpu_isa_base = cpu_isa[:5]
|
||||
cpu_isa_extensions = "\"i\"" # default
|
||||
# Append with optionals
|
||||
if "m" in cpu_isa[5:]:
|
||||
cpu_isa_extensions += ", \"m\""
|
||||
if "a" in cpu_isa[5:]:
|
||||
cpu_isa_extensions += ", \"a\""
|
||||
if "f" in cpu_isa[5:]:
|
||||
cpu_isa_extensions += ", \"f\""
|
||||
if "d" in cpu_isa[5:]:
|
||||
cpu_isa_extensions += ", \"d\""
|
||||
if "d" in cpu_isa[5:]:
|
||||
cpu_isa_extensions += ", \"c\""
|
||||
# rocket specific extensions
|
||||
if "rocket" in cpu_name:
|
||||
cpu_isa_extensions += ", \"zicsr\", \"zifencei\", \"zihpm\""
|
||||
|
||||
cpu_mmu = d["constants"].get("config_cpu_mmu", None)
|
||||
|
||||
# Header ---------------------------------------------------------------------------------------
|
||||
|
|
@ -152,7 +171,6 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
|
|||
|
||||
# Rocket specific attributes
|
||||
if ("rocket" in cpu_name):
|
||||
cpu_isa = cpu_isa.replace("2p0_", "")
|
||||
extra_attr = """
|
||||
hardware-exec-breakpoint-count = <1>;
|
||||
next-level-cache = <&memory>;
|
||||
|
|
@ -190,6 +208,8 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
|
|||
device_type = "cpu";
|
||||
compatible = "riscv";
|
||||
riscv,isa = "{cpu_isa}";
|
||||
riscv,isa-base = "{cpu_isa_base}";
|
||||
riscv,isa-extensions = {cpu_isa_extensions};
|
||||
mmu-type = "riscv,{cpu_mmu}";
|
||||
reg = <{cpu}>;
|
||||
clock-frequency = <{sys_clk_freq}>;
|
||||
|
|
@ -205,12 +225,14 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
|
|||
}};
|
||||
}};
|
||||
""".format(cpu=cpu, irq=cpu,
|
||||
sys_clk_freq = d["constants"]["config_clock_frequency"],
|
||||
cpu_isa = cpu_isa,
|
||||
cpu_mmu = cpu_mmu,
|
||||
cache_desc = cache_desc,
|
||||
tlb_desc = tlb_desc,
|
||||
extra_attr = extra_attr)
|
||||
sys_clk_freq = d["constants"]["config_clock_frequency"],
|
||||
cpu_isa = cpu_isa, # for kernel < 6.6.0
|
||||
cpu_isa_base = cpu_isa_base, # for kernel >= 6.6.0
|
||||
cpu_isa_extensions = cpu_isa_extensions, # for kernel >= 6.6.0
|
||||
cpu_mmu = cpu_mmu,
|
||||
cache_desc = cache_desc,
|
||||
tlb_desc = tlb_desc,
|
||||
extra_attr = extra_attr)
|
||||
dts += """
|
||||
{cpu_map}
|
||||
}};
|
||||
|
|
@ -381,6 +403,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
|
|||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
it_incr = {True: 1, False: 0}["rocket" in cpu_name]
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
compatible = "litex,liteuart";
|
||||
|
|
@ -390,15 +413,15 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
|
|||
}};
|
||||
""".format(
|
||||
uart_csr_base = d["csr_bases"]["uart"],
|
||||
uart_interrupt = "" if polling else "interrupts = <{}>;".format(d["constants"]["uart_interrupt"]))
|
||||
uart_interrupt = "" if polling else "interrupts = <{}>;".format(int(d["constants"]["uart_interrupt"]) + it_incr))
|
||||
|
||||
# Ethernet -------------------------------------------------------------------------------------
|
||||
for i in [''] + list(range(0, 10)):
|
||||
idx = (0 if i == '' else i)
|
||||
ethphy_name = "ethphy" + str(i)
|
||||
ethmac_name = "ethmac" + str(i)
|
||||
it_incr = {True: 1, False: 0}["rocket" in cpu_name]
|
||||
if ethphy_name in d["csr_bases"] and ethmac_name in d["csr_bases"]:
|
||||
|
||||
dts += """
|
||||
mac{idx}: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
|
|
@ -421,7 +444,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
|
|||
ethmac_rx_slots = d["constants"][ethmac_name + "_rx_slots"],
|
||||
ethmac_tx_slots = d["constants"][ethmac_name + "_tx_slots"],
|
||||
ethmac_slot_size = d["constants"][ethmac_name + "_slot_size"],
|
||||
ethmac_interrupt = "" if polling else "interrupts = <{}>;".format(d["constants"][ethmac_name + "_interrupt"]))
|
||||
ethmac_interrupt = "" if polling else "interrupts = <{}>;".format(int(d["constants"][ethmac_name + "_interrupt"]) + it_incr))
|
||||
|
||||
# USB OHCI -------------------------------------------------------------------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -178,6 +178,7 @@ class SimSoC(SoCCore):
|
|||
with_gpio = False,
|
||||
with_video_framebuffer = False,
|
||||
with_video_terminal = False,
|
||||
with_video_colorbars = False,
|
||||
sim_debug = False,
|
||||
trace_reset_on = False,
|
||||
with_jtag = False,
|
||||
|
|
@ -313,6 +314,11 @@ class SimSoC(SoCCore):
|
|||
self.submodules.videophy = VideoGenericPHY(platform.request("vga"))
|
||||
self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz")
|
||||
|
||||
# Video test pattern -----------------------------------------------------------------------
|
||||
if with_video_colorbars:
|
||||
self.submodules.videophy = VideoGenericPHY(platform.request("vga"))
|
||||
self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz")
|
||||
|
||||
# Simulation debugging ----------------------------------------------------------------------
|
||||
if sim_debug:
|
||||
platform.add_debug(self, reset=1 if trace_reset_on else 0)
|
||||
|
|
@ -428,6 +434,8 @@ def sim_args(parser):
|
|||
# Video.
|
||||
parser.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer.")
|
||||
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.")
|
||||
parser.add_argument("--with-video-colorbars", action="store_true", help="Enable Video test pattern.")
|
||||
parser.add_argument("--video-vsync", action="store_true", help="Only render on frame vsync.")
|
||||
|
||||
# Debug/Waveform.
|
||||
parser.add_argument("--sim-debug", action="store_true", help="Add simulation debugging modules.")
|
||||
|
|
@ -510,8 +518,8 @@ def main():
|
|||
sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
|
||||
|
||||
# Video.
|
||||
if args.with_video_framebuffer or args.with_video_terminal:
|
||||
sim_config.add_module("video", "vga")
|
||||
if args.with_video_framebuffer or args.with_video_terminal or args.with_video_colorbars:
|
||||
sim_config.add_module("video", "vga", args={"render_on_vsync": args.video_vsync})
|
||||
|
||||
# SoC ------------------------------------------------------------------------------------------
|
||||
soc = SimSoC(
|
||||
|
|
@ -528,6 +536,7 @@ def main():
|
|||
with_gpio = args.with_gpio,
|
||||
with_video_framebuffer = args.with_video_framebuffer,
|
||||
with_video_terminal = args.with_video_terminal,
|
||||
with_video_colorbars = args.with_video_colorbars,
|
||||
sim_debug = args.sim_debug,
|
||||
trace_reset_on = int(float(args.trace_start)) > 0 or int(float(args.trace_end)) > 0,
|
||||
spi_flash_init = None if args.spi_flash_init is None else get_mem_data(args.spi_flash_init, endianness="big"),
|
||||
|
|
@ -551,7 +560,7 @@ def main():
|
|||
builder.build(
|
||||
sim_config = sim_config,
|
||||
interactive = not args.non_interactive,
|
||||
video = args.with_video_framebuffer or args.with_video_terminal,
|
||||
video = args.with_video_framebuffer or args.with_video_terminal or args.with_video_colorbars,
|
||||
pre_run_callback = pre_run_callback,
|
||||
**parser.toolchain_argdict,
|
||||
)
|
||||
|
|
|
|||
Loading…
Reference in New Issue