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soc/add_sata: Add IRQ support.

This commit is contained in:
Florent Kermarrec 2022-05-18 15:05:00 +02:00
parent 4401b5a5e8
commit 5df1f5f511
1 changed files with 14 additions and 0 deletions
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14
litex/soc/integration/soc.py
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@ -1818,6 +1818,20 @@ class LiteXSoC(SoC):
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sata_mem2sector", master=bus) dma_bus.add_master("sata_mem2sector", master=bus)
# Interrupts.
self.submodules.sata_irq = EventManager()
if "read" in mode:
self.sata_irq.sector2mem_dma = EventSourcePulse(description="Sector2Mem DMA terminated.")
if "write" in mode:
self.sata_irq.mem2sector_dma = EventSourcePulse(description="Mem2Sector DMA terminated.")
self.sata_irq.finalize()
if "read" in mode:
self.comb += self.sata_irq.sector2mem_dma.trigger.eq(self.sata_sector2mem.irq)
if "write" in mode:
self.comb += self.sata_irq.mem2sector_dma.trigger.eq(self.sata_mem2sector.irq)
if self.irq.enabled:
self.irq.add("sata", use_loc_if_exists=True)
# Timing constraints. # Timing constraints.
self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/sata_clk_freq) self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/sata_clk_freq)
self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk, 1e9/sata_clk_freq) self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk, 1e9/sata_clk_freq)