Provide a deployable naxriscv SMP
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@ -153,12 +153,18 @@ class NaxRiscv(CPU):
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# # #
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self.tracer_valid = Signal()
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self.tracer_payload = Signal(8)
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# CPU Instance.
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self.cpu_params = dict(
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# Clk/Rst.
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i_clk = ClockSignal("sys"),
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i_reset = ResetSignal("sys") | self.reset,
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o_patcher_tracer_valid=self.tracer_valid,
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o_patcher_tracer_payload=self.tracer_payload,
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# Interrupt.
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i_peripheral_externalInterrupts_port = self.interrupt,
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@ -289,9 +295,9 @@ class NaxRiscv(CPU):
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ndir = os.path.join(vdir, "ext", "NaxRiscv")
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sdir = os.path.join(vdir, "ext", "SpinalHDL")
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# if NaxRiscv.update_repo != "no":
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# NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "57e3bf59" if NaxRiscv.update_repo=="recommended" else None)
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# NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "8511f126" if NaxRiscv.update_repo=="recommended" else None)
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if NaxRiscv.update_repo != "no":
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NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "coherency", "abe0c3bc" if NaxRiscv.update_repo=="recommended" else None)
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NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "bus-fabric" , "d1f0b637" if NaxRiscv.update_repo=="recommended" else None)
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gen_args = []
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gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
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