gen: add missing sim files
This commit is contained in:
Florent Kermarrec
parent
dd2397b57c
commit
5e16516706
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@ -0,0 +1,372 @@
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import operator
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import collections
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import inspect
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from functools import wraps
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from litex.gen.fhdl.structure import *
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from litex.gen.fhdl.structure import (_Value, _Statement,
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_Operator, _Slice, _ArrayProxy,
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_Assign, _Fragment)
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from litex.gen.fhdl.bitcontainer import value_bits_sign
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from litex.gen.fhdl.tools import (list_targets, list_signals,
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insert_resets, lower_specials)
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from litex.gen.fhdl.simplify import MemoryToArray
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from litex.gen.fhdl.specials import _MemoryLocation
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from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter
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class ClockState:
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def __init__(self, high, half_period, time_before_trans):
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self.high = high
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self.half_period = half_period
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self.time_before_trans = time_before_trans
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class TimeManager:
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def __init__(self, description):
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self.clocks = collections.OrderedDict()
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for k, period_phase in description.items():
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if isinstance(period_phase, tuple):
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period, phase = period_phase
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else:
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period = period_phase
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phase = 0
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half_period = period//2
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if phase >= half_period:
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phase -= half_period
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high = True
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else:
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high = False
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self.clocks[k] = ClockState(high, half_period, half_period - phase)
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def tick(self):
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rising = set()
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falling = set()
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dt = min(cs.time_before_trans for cs in self.clocks.values())
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for k, cs in self.clocks.items():
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if cs.time_before_trans == dt:
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cs.high = not cs.high
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if cs.high:
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rising.add(k)
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else:
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falling.add(k)
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cs.time_before_trans -= dt
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if not cs.time_before_trans:
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cs.time_before_trans += cs.half_period
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return dt, rising, falling
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str2op = {
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"~": operator.invert,
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"+": operator.add,
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"-": operator.sub,
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"*": operator.mul,
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">>>": operator.rshift,
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"<<<": operator.lshift,
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"&": operator.and_,
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"^": operator.xor,
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"|": operator.or_,
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"<": operator.lt,
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"<=": operator.le,
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"==": operator.eq,
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"!=": operator.ne,
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">": operator.gt,
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">=": operator.ge,
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}
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def _truncate(value, nbits, signed):
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value = value & (2**nbits - 1)
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if signed and (value & 2**(nbits - 1)):
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value -= 2**nbits
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return value
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class Evaluator:
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def __init__(self, clock_domains, replaced_memories):
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self.clock_domains = clock_domains
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self.replaced_memories = replaced_memories
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self.signal_values = dict()
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self.modifications = dict()
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def commit(self):
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r = set()
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for k, v in self.modifications.items():
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if k not in self.signal_values or self.signal_values[k] != v:
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self.signal_values[k] = v
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r.add(k)
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self.modifications.clear()
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return r
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def eval(self, node, postcommit=False):
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if isinstance(node, Constant):
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return node.value
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elif isinstance(node, Signal):
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if postcommit:
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try:
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return self.modifications[node]
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except KeyError:
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pass
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try:
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return self.signal_values[node]
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except KeyError:
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return node.reset.value
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elif isinstance(node, _Operator):
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operands = [self.eval(o, postcommit) for o in node.operands]
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if node.op == "-":
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if len(operands) == 1:
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return -operands[0]
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else:
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return operands[0] - operands[1]
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elif node.op == "m":
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return operands[1] if operands[0] else operands[2]
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else:
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return str2op[node.op](*operands)
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elif isinstance(node, _Slice):
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v = self.eval(node.value, postcommit)
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idx = range(node.start, node.stop)
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return sum(((v >> i) & 1) << j for j, i in enumerate(idx))
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elif isinstance(node, Cat):
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shift = 0
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r = 0
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for element in node.l:
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nbits = len(element)
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# make value always positive
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r |= (self.eval(element, postcommit) & (2**nbits-1)) << shift
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shift += nbits
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return r
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elif isinstance(node, Replicate):
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nbits = len(node.v)
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v = self.eval(node.v, postcommit) & (2**nbits - 1)
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return sum(v << i*nbits for i in range(node.n))
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elif isinstance(node, _ArrayProxy):
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return self.eval(node.choices[self.eval(node.key, postcommit)],
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postcommit)
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elif isinstance(node, _MemoryLocation):
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array = self.replaced_memories[node.memory]
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return self.eval(array[self.eval(node.index, postcommit)], postcommit)
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elif isinstance(node, ClockSignal):
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return self.eval(self.clock_domains[node.cd].clk, postcommit)
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elif isinstance(node, ResetSignal):
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rst = self.clock_domains[node.cd].rst
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if rst is None:
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if node.allow_reset_less:
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return 0
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else:
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raise ValueError("Attempted to get reset signal of resetless"
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" domain '{}'".format(node.cd))
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else:
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return self.eval(rst, postcommit)
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else:
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raise NotImplementedError(node)
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def assign(self, node, value):
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if isinstance(node, Signal):
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assert not node.variable
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self.modifications[node] = _truncate(value,
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node.nbits, node.signed)
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elif isinstance(node, Cat):
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for element in node.l:
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nbits = len(element)
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self.assign(element, value & (2**nbits-1))
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value >>= nbits
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elif isinstance(node, _Slice):
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full_value = self.eval(node.value, True)
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# clear bits assigned to by the slice
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full_value &= ~((2**node.stop-1) - (2**node.start-1))
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# set them to the new value
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value &= 2**(node.stop - node.start)-1
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full_value |= value << node.start
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self.assign(node.value, full_value)
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elif isinstance(node, _ArrayProxy):
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self.assign(node.choices[self.eval(node.key)], value)
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elif isinstance(node, _MemoryLocation):
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array = self.replaced_memories[node.memory]
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self.assign(array[self.eval(node.index)], value)
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else:
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raise NotImplementedError(node)
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def execute(self, statements):
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for s in statements:
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if isinstance(s, _Assign):
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self.assign(s.l, self.eval(s.r))
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elif isinstance(s, If):
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if self.eval(s.cond) & (2**len(s.cond) - 1):
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self.execute(s.t)
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else:
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self.execute(s.f)
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elif isinstance(s, Case):
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nbits, signed = value_bits_sign(s.test)
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test = _truncate(self.eval(s.test), nbits, signed)
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found = False
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for k, v in s.cases.items():
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if isinstance(k, Constant) and k.value == test:
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self.execute(v)
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found = True
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break
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if not found and "default" in s.cases:
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self.execute(s.cases["default"])
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elif isinstance(s, collections.Iterable):
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self.execute(s)
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else:
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raise NotImplementedError
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# TODO: instances via Iverilog/VPI
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class Simulator:
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def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=None):
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if isinstance(fragment_or_module, _Fragment):
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self.fragment = fragment_or_module
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else:
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self.fragment = fragment_or_module.get_fragment()
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mta = MemoryToArray()
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mta.transform_fragment(None, self.fragment)
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fs, lowered = lower_specials(overrides={}, specials=self.fragment.specials)
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self.fragment += fs
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self.fragment.specials -= lowered
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if self.fragment.specials:
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raise ValueError("Could not lower all specials", self.fragment.specials)
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if not isinstance(generators, dict):
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generators = {"sys": generators}
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self.generators = dict()
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self.passive_generators = set()
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for k, v in generators.items():
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if (isinstance(v, collections.Iterable)
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and not inspect.isgenerator(v)):
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self.generators[k] = list(v)
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else:
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self.generators[k] = [v]
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clocks = collections.OrderedDict(sorted(clocks.items(),
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key=operator.itemgetter(0)))
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self.time = TimeManager(clocks)
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for clock in clocks.keys():
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if clock not in self.fragment.clock_domains:
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cd = ClockDomain(name=clock, reset_less=True)
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cd.clk.reset = C(self.time.clocks[clock].high)
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self.fragment.clock_domains.append(cd)
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insert_resets(self.fragment)
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# comb signals return to their reset value if nothing assigns them
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self.fragment.comb[0:0] = [s.eq(s.reset)
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for s in list_targets(self.fragment.comb)]
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self.evaluator = Evaluator(self.fragment.clock_domains,
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mta.replacements)
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if vcd_name is None:
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self.vcd = DummyVCDWriter()
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else:
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self.vcd = VCDWriter(vcd_name)
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signals = list_signals(self.fragment)
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for cd in self.fragment.clock_domains:
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signals.add(cd.clk)
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if cd.rst is not None:
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signals.add(cd.rst)
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for memory_array in mta.replacements.values():
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signals |= set(memory_array)
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for signal in sorted(signals, key=lambda x: x.duid):
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self.vcd.set(signal, signal.reset.value)
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def __enter__(self):
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return self
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def __exit__(self, type, value, traceback):
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self.close()
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def close(self):
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self.vcd.close()
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def _commit_and_comb_propagate(self):
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# TODO: optimize
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all_modified = set()
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modified = self.evaluator.commit()
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all_modified |= modified
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while modified:
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self.evaluator.execute(self.fragment.comb)
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modified = self.evaluator.commit()
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all_modified |= modified
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for signal in all_modified:
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self.vcd.set(signal, self.evaluator.signal_values[signal])
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def _evalexec_nested_lists(self, x):
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if isinstance(x, list):
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return [self._evalexec_nested_lists(e) for e in x]
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elif isinstance(x, _Value):
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return self.evaluator.eval(x)
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elif isinstance(x, _Statement):
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self.evaluator.execute([x])
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return None
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else:
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raise ValueError
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def _process_generators(self, cd):
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exhausted = []
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for generator in self.generators[cd]:
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reply = None
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while True:
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try:
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request = generator.send(reply)
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if request is None:
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break # next cycle
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elif isinstance(request, str):
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if request == "passive":
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self.passive_generators.add(generator)
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elif request == "active":
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self.passive_generators.discard(generator)
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else:
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raise ValueError("Unknown simulator command: '{}'"
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.format(request))
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else:
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reply = self._evalexec_nested_lists(request)
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except StopIteration:
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exhausted.append(generator)
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break
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for generator in exhausted:
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self.generators[cd].remove(generator)
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def _continue_simulation(self):
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for cd_generators in self.generators.values():
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if set(cd_generators) - self.passive_generators:
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return True
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return False
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def run(self):
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self.evaluator.execute(self.fragment.comb)
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self._commit_and_comb_propagate()
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while True:
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dt, rising, falling = self.time.tick()
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self.vcd.delay(dt)
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for cd in rising:
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self.evaluator.assign(self.fragment.clock_domains[cd].clk, 1)
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if cd in self.fragment.sync:
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self.evaluator.execute(self.fragment.sync[cd])
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if cd in self.generators:
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self._process_generators(cd)
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for cd in falling:
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self.evaluator.assign(self.fragment.clock_domains[cd].clk, 0)
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self._commit_and_comb_propagate()
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if not self._continue_simulation():
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break
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def run_simulation(*args, **kwargs):
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with Simulator(*args, **kwargs) as s:
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s.run()
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def passive(generator):
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@wraps(generator)
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def wrapper(*args, **kwargs):
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yield "passive"
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yield from generator(*args, **kwargs)
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return wrapper
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@ -0,0 +1,85 @@
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from itertools import count
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import tempfile
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import os
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from collections import OrderedDict
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import shutil
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from litex.gen.fhdl.namer import build_namespace
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def vcd_codes():
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codechars = [chr(i) for i in range(33, 127)]
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for n in count():
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q, r = divmod(n, len(codechars))
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code = codechars[r]
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while q > 0:
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q, r = divmod(q, len(codechars))
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code = codechars[r] + code
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yield code
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class VCDWriter:
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def __init__(self, filename):
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self.filename = filename
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self.buffer_file = tempfile.TemporaryFile(
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dir=os.path.dirname(filename), mode="w+")
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self.codegen = vcd_codes()
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self.codes = OrderedDict()
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self.signal_values = dict()
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self.t = 0
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def _write_value(self, f, signal, value):
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l = len(signal)
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if value < 0:
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value += 2**l
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if l > 1:
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fmtstr = "b{:0" + str(l) + "b} {}\n"
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else:
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fmtstr = "{}{}\n"
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try:
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code = self.codes[signal]
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except KeyError:
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code = next(self.codegen)
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self.codes[signal] = code
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f.write(fmtstr.format(value, code))
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def set(self, signal, value):
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if (signal not in self.signal_values
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or self.signal_values[signal] != value):
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self._write_value(self.buffer_file, signal, value)
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self.signal_values[signal] = value
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def delay(self, delay):
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self.t += delay
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self.buffer_file.write("#{}\n".format(self.t))
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def close(self):
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out = open(self.filename, "w")
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try:
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ns = build_namespace(self.codes.keys())
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for signal, code in self.codes.items():
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name = ns.get_name(signal)
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out.write("$var wire {len} {code} {name} $end\n"
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.format(name=name, code=code, len=len(signal)))
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out.write("$dumpvars\n")
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for signal in self.codes.keys():
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self._write_value(out, signal, signal.reset.value)
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out.write("$end\n")
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out.write("#0\n")
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self.buffer_file.seek(0)
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shutil.copyfileobj(self.buffer_file, out)
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self.buffer_file.close()
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finally:
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out.close()
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class DummyVCDWriter:
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def set(self, signal, value):
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pass
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def delay(self, delay):
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pass
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def close(self):
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pass
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