README.md: IRC channel moved to moved to irc.libera.chat (https://libera.chat) #litex due to staff issues.
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@ -16,7 +16,7 @@ SoC builder to create/develop/debug FPGA SoCs in Python.
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**Want to get started and/or looking for documentation? Make sure to visit the [Wiki](https://github.com/enjoy-digital/litex/wiki)!**
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**Want to get started and/or looking for documentation? Make sure to visit the [Wiki](https://github.com/enjoy-digital/litex/wiki)!**
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**A question or want to get in touch? Our IRC channel is [#litex at freenode.net](https://webchat.freenode.net/?channels=litex)**
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**A question or want to get in touch? Our IRC channel is [#litex at irc.libera.chat]**
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# Typical LiteX design flow:
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# Typical LiteX design flow:
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```
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```
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