core/naxriscv switch to main branch, and implement a reset controller internaly
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@ -165,8 +165,8 @@ class NaxRiscv(CPU):
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# CPU Instance.
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self.cpu_params = dict(
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# Clk/Rst.
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i_clk = ClockSignal("sys"),
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i_reset = ResetSignal("sys") | self.reset,
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i_socClk = ClockSignal("sys"),
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i_asyncReset = ResetSignal("sys") | self.reset,
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o_patcher_tracer_valid=self.tracer_valid,
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o_patcher_tracer_payload=self.tracer_payload,
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@ -308,8 +308,7 @@ class NaxRiscv(CPU):
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sdir = os.path.join(vdir, "ext", "SpinalHDL")
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if NaxRiscv.update_repo != "no":
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NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "coherency", "9e44c1b6" if NaxRiscv.update_repo=="recommended" else None)
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NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "bus-fabric" , "74c5d7de" if NaxRiscv.update_repo=="recommended" else None)
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NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "b6d0712f" if NaxRiscv.update_repo=="recommended" else None)
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gen_args = []
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gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
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