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soc/intergration/soc/add_pcie: Add new status_width parameter.

This commit is contained in:
Florent Kermarrec 2024-09-27 11:46:19 +02:00
parent 644ef7e4e5
commit 5e897752b7
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc.py
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@ -2395,7 +2395,7 @@ class LiteXSoC(SoC):
with_dma_loopback = True, with_dma_loopback = True,
with_dma_synchronizer = False, with_dma_synchronizer = False,
with_dma_monitor = False, with_dma_monitor = False,
with_dma_status = False, with_dma_status = False, status_width=32,
with_dma_table = True, with_dma_table = True,
with_msi = True, msi_type="msi", msi_width=32, msis={}, with_msi = True, msi_type="msi", msi_width=32, msis={},
with_ptm = False, with_ptm = False,
@ -2450,7 +2450,7 @@ class LiteXSoC(SoC):
with_loopback = with_dma_loopback, with_loopback = with_dma_loopback,
with_synchronizer = with_dma_synchronizer, with_synchronizer = with_dma_synchronizer,
with_monitor = with_dma_monitor, with_monitor = with_dma_monitor,
with_status = with_dma_status, with_status = with_dma_status, status_width=status_width,
with_table = with_dma_table, with_table = with_dma_table,
address_width = address_width, address_width = address_width,
data_width = data_width, data_width = data_width,