software/liblitedram/sdram: improve comments.
This commit is contained in:
Florent Kermarrec
parent
44d21cb0f3
commit
5ebea9434b
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@ -325,10 +325,10 @@ static void sdram_write_leveling_rst_delay(int module) {
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int i;
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#endif
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/* sel module */
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/* Select module */
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ddrphy_dly_sel_write(1 << module);
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/* rst delay */
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/* Reset delay */
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ddrphy_wdly_dq_rst_write(1);
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ddrphy_wdly_dqs_rst_write(1);
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cdelay(100);
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@ -339,19 +339,19 @@ static void sdram_write_leveling_rst_delay(int module) {
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}
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#endif
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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}
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static void sdram_write_leveling_inc_delay(int module) {
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/* sel module */
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/* Select module */
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ddrphy_dly_sel_write(1 << module);
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/* inc delay */
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/* Increment delay */
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ddrphy_wdly_dq_inc_write(1);
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ddrphy_wdly_dqs_inc_write(1);
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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}
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@ -379,11 +379,11 @@ static int sdram_write_leveling_scan(int *delays, int loops, int show)
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if (show)
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printf(" m%d: |", i);
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/* rst delay */
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/* Reset delay */
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sdram_write_leveling_rst_delay(i);
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cdelay(100);
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/* scan write delay taps */
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/* Scan write delay taps */
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for(j=0;j<err_ddrphy_wdly;j++) {
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int zero_count = 0;
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int one_count = 0;
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@ -412,7 +412,7 @@ static int sdram_write_leveling_scan(int *delays, int loops, int show)
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if (show)
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printf("|");
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/* find longer 1 window and set delay at the 0/1 transition */
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/* Find longer 1 window and set delay at the 0/1 transition */
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one_window_active = 0;
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one_window_start = 0;
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one_window_count = 0;
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@ -437,24 +437,24 @@ static int sdram_write_leveling_scan(int *delays, int loops, int show)
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}
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}
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/* rst delay */
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/* Reset delay */
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sdram_write_leveling_rst_delay(i);
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cdelay(100);
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/* use forced delay if configured */
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/* Use forced delay if configured */
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if (_sdram_write_leveling_dat_delays[i] >= 0) {
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delays[i] = _sdram_write_leveling_dat_delays[i];
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/* configure write delay */
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/* Configure write delay */
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for(j=0; j<delays[i]; j++) {
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sdram_write_leveling_inc_delay(i);
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cdelay(100);
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}
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/* succeed only if the start of a 1s window has been found */
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/* Succeed only if the start of a 1s window has been found */
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} else if (one_window_best_count > 0 && one_window_best_start > 0) {
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delays[i] = one_window_best_start;
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/* configure write delay */
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/* Configure write delay */
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for(j=0; j<delays[i]; j++) {
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sdram_write_leveling_inc_delay(i);
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cdelay(100);
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@ -486,27 +486,27 @@ static void sdram_write_leveling_find_cmd_delay(unsigned int *best_error, int *b
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int cdly_actual = 0;
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int delays[SDRAM_PHY_MODULES];
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/* scan through the range */
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/* Scan through the range */
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ddrphy_cdly_rst_write(1);
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cdelay(100);
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for (cdly = cdly_start; cdly < cdly_stop; cdly += cdly_step) {
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/* increment cdly to current value */
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/* Increment cdly to current value */
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while (cdly_actual < cdly) {
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ddrphy_cdly_inc_write(1);
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cdelay(100);
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cdly_actual++;
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}
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/* write level using this delay */
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/* Write level using this delay */
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if (sdram_write_leveling_scan(delays, 8, 0)) {
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/* use the mean of delays for error calulation */
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/* Use the mean of delays for error calulation */
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int delay_mean = 0;
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for (int i=0; i < SDRAM_PHY_MODULES; ++i) {
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delay_mean += delays[i];
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}
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delay_mean /= SDRAM_PHY_MODULES;
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/* we want it to be at the start */
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/* We want it to be at the start */
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int ideal_delay = 4*SDRAM_PHY_DELAYS/32;
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int error = ideal_delay - delay_mean;
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if (error < 0)
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@ -548,11 +548,11 @@ int sdram_write_leveling(void)
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sdram_write_leveling_find_cmd_delay(&best_error, &best_cdly,
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cdly_range_start, cdly_range_end, cdly_range_step);
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/* small optimization - stop if we have zero error */
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/* Small optimization - stop if we have zero error */
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if (best_error == 0)
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break;
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/* use best result as the middle of next range */
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/* Use best result as the middle of next range */
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cdly_range_start = best_cdly - cdly_range_step;
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cdly_range_end = best_cdly + cdly_range_step + 1;
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if (cdly_range_start < 0)
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@ -567,7 +567,7 @@ int sdram_write_leveling(void)
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best_cdly = _sdram_write_leveling_cmd_delay;
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}
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printf(" Setting Cmd/Clk delay to %d taps.\n", best_cdly);
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/* set working or forced delay */
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/* Set working or forced delay */
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if (best_cdly >= 0) {
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ddrphy_cdly_rst_write(1);
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cdelay(100);
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@ -579,7 +579,7 @@ int sdram_write_leveling(void)
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printf(" Data scan:\n");
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/* re-run write leveling the final time */
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/* Re-run write leveling the final time */
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if (!sdram_write_leveling_scan(delays, 128, 1))
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return 0;
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@ -593,13 +593,13 @@ int sdram_write_leveling(void)
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/*-----------------------------------------------------------------------*/
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static void sdram_read_leveling_rst_delay(int module) {
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/* sel module */
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/* Select module */
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ddrphy_dly_sel_write(1 << module);
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/* rst delay */
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/* Reset delay */
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ddrphy_rdly_dq_rst_write(1);
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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#ifdef SDRAM_PHY_ECP5DDRPHY
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@ -610,13 +610,13 @@ static void sdram_read_leveling_rst_delay(int module) {
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}
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static void sdram_read_leveling_inc_delay(int module) {
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/* sel module */
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/* Select module */
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ddrphy_dly_sel_write(1 << module);
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/* inc delay */
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/* Increment delay */
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ddrphy_rdly_dq_inc_write(1);
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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#ifdef SDRAM_PHY_ECP5DDRPHY
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@ -628,26 +628,26 @@ static void sdram_read_leveling_inc_delay(int module) {
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static void sdram_read_leveling_rst_bitslip(char m)
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{
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/* sel module */
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/* Select module */
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ddrphy_dly_sel_write(1 << m);
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/* rst delay */
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/* Reset delay */
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ddrphy_rdly_dq_bitslip_rst_write(1);
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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}
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static void sdram_read_leveling_inc_bitslip(char m)
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{
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/* sel module */
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/* Select module */
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ddrphy_dly_sel_write(1 << m);
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/* inc delay */
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/* Increment delay */
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ddrphy_rdly_dq_bitslip_write(1);
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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}
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@ -877,14 +877,14 @@ static void sdram_write_latency_calibration(void) {
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best_bitslip = 0;
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for(bitslip=0; bitslip<SDRAM_PHY_BITSLIPS; bitslip+=2) { /* +2 for tCK steps */
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score = 0;
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/* sel module */
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/* Select module */
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ddrphy_dly_sel_write(1 << module);
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/* rst bitslip */
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/* Reset bitslip */
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ddrphy_wdly_dq_bitslip_rst_write(1);
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for (i=0; i<bitslip; i++) {
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ddrphy_wdly_dq_bitslip_write(1);
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}
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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score = 0;
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sdram_read_leveling_rst_bitslip(module);
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@ -908,12 +908,13 @@ static void sdram_write_latency_calibration(void) {
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/* Select best write window */
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ddrphy_dly_sel_write(1 << module);
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/* rst bitslip */
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/* Reset bitslip */
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ddrphy_wdly_dq_bitslip_rst_write(1);
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for (i=0; i<bitslip; i++) {
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ddrphy_wdly_dq_bitslip_write(1);
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}
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/* unsel module */
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/* Un-select module */
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ddrphy_dly_sel_write(0);
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}
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printf("\n");
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