efinix: add io bank voltage configuration
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@ -295,9 +295,10 @@ class EfinityToolchain:
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excluded_ios = self.excluded_ios
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)
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# DDR doesn't have Python API so we need to configure it
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# Some IO blocks don't have Python API so we need to configure them
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# directly in the peri.xml file
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if self.ifacewriter.xml_blocks:
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# We also need to configure the bank voltage here
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if self.ifacewriter.xml_blocks or platform.iobank_info:
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self.ifacewriter.generate_xml_blocks()
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# Run
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@ -57,6 +57,9 @@ class InterfaceWriter:
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if block["type"] == "DRAM":
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self.add_dram_xml(root, block)
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if self.platform.iobank_info:
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self.add_iobank_info_xml(root, self.platform.iobank_info)
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xml_string = et.tostring(root, "utf-8")
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reparsed = expatbuilder.parseString(xml_string, False)
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print_string = reparsed.toprettyxml(indent=" ")
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@ -282,3 +285,10 @@ design.save()"""
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load = "3"
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)
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def add_iobank_info_xml(self, root, iobank_info):
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dev = root.find("efxpt:device_info", namespaces)
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bank_info = dev.find("efxpt:iobank_info", namespaces)
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for name, iostd in iobank_info:
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for child in bank_info:
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if name == child.get("name"):
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child.set("iostd", iostd)
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@ -18,11 +18,12 @@ from litex.build.efinix import EfinixDbParser
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class EfinixPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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def __init__(self, *args, toolchain="efinity", **kwargs):
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def __init__(self, *args, iobank_info=None, toolchain="efinity", **kwargs):
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GenericPlatform.__init__(self, *args, **kwargs)
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self.timing_model = self.device[-2:]
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self.device = self.device[:-2]
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self.iobank_info = iobank_info
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if os.getenv("LITEX_ENV_EFINITY", False) == False:
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msg = "Unable to find or source Efinity toolchain, please either:\n"
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