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global: pep8 (E225)

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This commit is contained in:
Florent Kermarrec 2015-04-13 21:11:13 +02:00
parent 728c15213f
commit 5f225c0475
4 changed files with 19 additions and 19 deletions
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2
mibuild/altera/quartus.py
View file

@ -51,7 +51,7 @@ def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
# Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog) # Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
if language == "verilog": if language == "verilog":
language = "systemverilog" language = "systemverilog"
qsf_contents += "set_global_assignment -name "+ language.upper() + "_FILE " + filename.replace("\\", "/") + "\n" qsf_contents += "set_global_assignment -name " + language.upper() + "_FILE " + filename.replace("\\", "/") + "\n"
for path in vincpaths: for path in vincpaths:
qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\", "/") + "\n" qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\", "/") + "\n"

2
mibuild/lattice/diamond.py
View file

@ -45,7 +45,7 @@ def _build_lpf(named_sc, named_pc):
def _build_files(device, sources, vincpaths, build_name): def _build_files(device, sources, vincpaths, build_name):
tcl = [] tcl = []
tcl.append("prj_project new -name \"%s\" -impl \"implementation\" -dev %s -synthesis \"synplify\"" %(build_name, device)) tcl.append("prj_project new -name \"{}\" -impl \"implementation\" -dev {} -synthesis \"synplify\"".format(build_name, device))
for path in vincpaths: for path in vincpaths:
tcl.append("prj_impl option {include path} {\"" + path.replace("\\", "/") + "\"}") tcl.append("prj_impl option {include path} {\"" + path.replace("\\", "/") + "\"}")
for filename, language in sources: for filename, language in sources:

32
mibuild/xilinx/vivado.py
View file

@ -23,7 +23,7 @@ def _format_constraint(c):
elif isinstance(c, Misc): elif isinstance(c, Misc):
return "set_property " + c.misc.replace("=", " ") return "set_property " + c.misc.replace("=", " ")
else: else:
raise ValueError("unknown constraint %s" % c) raise ValueError("unknown constraint {}".format(c))
def _format_xdc(signame, resname, *constraints): def _format_xdc(signame, resname, *constraints):
@ -31,7 +31,7 @@ def _format_xdc(signame, resname, *constraints):
fmt_r = resname[0] + ":" + str(resname[1]) fmt_r = resname[0] + ":" + str(resname[1])
if resname[2] is not None: if resname[2] is not None:
fmt_r += "." + resname[2] fmt_r += "." + resname[2]
r = " ## %s\n" %fmt_r r = " ## {}\n".format(fmt_r)
for c in fmt_c: for c in fmt_c:
r += c + " [get_ports " + signame + "]\n" r += c + " [get_ports " + signame + "]\n"
return r return r
@ -84,27 +84,27 @@ class XilinxVivadoToolchain:
for filename, language in sources: for filename, language in sources:
tcl.append("add_files " + filename.replace("\\", "/")) tcl.append("add_files " + filename.replace("\\", "/"))
tcl.append("read_xdc %s.xdc" %build_name) tcl.append("read_xdc {}.xdc".format(build_name))
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(platform.device, " ".join(platform.verilog_include_paths))) tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths)))
tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_synth.rpt" %(build_name)) tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name)) tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
tcl.append("place_design") tcl.append("place_design")
if self.with_phys_opt: if self.with_phys_opt:
tcl.append("phys_opt_design -directive AddRetime") tcl.append("phys_opt_design -directive AddRetime")
tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_place.rpt" %(build_name)) tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name)) tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
tcl.append("report_io -file %s_io.rpt" %(build_name)) tcl.append("report_io -file {}_io.rpt".format(build_name))
tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name)) tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name)) tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
tcl.append("route_design") tcl.append("route_design")
tcl.append("report_route_status -file %s_route_status.rpt" %(build_name)) tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
tcl.append("report_drc -file %s_drc.rpt" %(build_name)) tcl.append("report_drc -file {}_drc.rpt".format(build_name))
tcl.append("report_timing_summary -max_paths 10 -file %s_timing.rpt" %(build_name)) tcl.append("report_timing_summary -max_paths 10 -file {}_timing.rpt".format(build_name))
tcl.append("report_power -file %s_power.rpt" %(build_name)) tcl.append("report_power -file {}_power.rpt".format(build_name))
for bitstream_command in self.bitstream_commands: for bitstream_command in self.bitstream_commands:
tcl.append(bitstream_command.format(build_name=build_name)) tcl.append(bitstream_command.format(build_name=build_name))
tcl.append("write_bitstream -force %s.bit " %build_name) tcl.append("write_bitstream -force {}.bit ".format(build_name))
for additional_command in self.additional_commands: for additional_command in self.additional_commands:
tcl.append(additional_command.format(build_name=build_name)) tcl.append(additional_command.format(build_name=build_name))
tcl.append("quit") tcl.append("quit")

2
migen/actorlib/spi.py
View file

@ -170,7 +170,7 @@ class DMAWriteController(_DMAController):
if ack_when_inactive: if ack_when_inactive:
demultiplexer = plumbing.Demultiplexer([("d", bus_dw)], 2) demultiplexer = plumbing.Demultiplexer([("d", bus_dw)], 2)
self.comb +=[ self.comb += [
demultiplexer.sel.eq(~adr_buffer.busy), demultiplexer.sel.eq(~adr_buffer.busy),
demultiplexer.source0.connect(comp_actor.d), demultiplexer.source0.connect(comp_actor.d),
demultiplexer.source1.ack.eq(1), demultiplexer.source1.ack.eq(1),