boards/nexys4ddr: add ethernet support (RMII 100Mbps)
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parent
0ba1cb8756
commit
5f6e787494
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@ -81,6 +81,24 @@ _io = [
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Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")),
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Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")),
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Misc("SLEW=FAST"),
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Misc("SLEW=FAST"),
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),
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),
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins("D5")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("B3")),
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Subsignal("rx_data", Pins("C11 D10")),
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Subsignal("crs_dv", Pins("D9")),
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Subsignal("tx_en", Pins("B9")),
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Subsignal("tx_data", Pins("A10 A8")),
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Subsignal("mdc", Pins("C9")),
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Subsignal("mdio", Pins("A9")),
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Subsignal("rx_er", Pins("C10")),
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Subsignal("int_n", Pins("D8")),
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IOStandard("LVCMOS33")
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),
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]
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]
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# Platform -----------------------------------------------------------------------------------------
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# Platform -----------------------------------------------------------------------------------------
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@ -14,6 +14,9 @@ from litex.soc.integration.builder import *
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from litedram.modules import MT47H64M16
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from litedram.modules import MT47H64M16
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from litedram.phy import s7ddrphy
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from litedram.phy import s7ddrphy
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from liteeth.phy.rmii import LiteEthPHYRMII
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from liteeth.core.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(Module):
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@ -22,6 +25,7 @@ class _CRG(Module):
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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# # #
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@ -36,6 +40,7 @@ class _CRG(Module):
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_eth, 50e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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@ -60,6 +65,37 @@ class BaseSoC(SoCSDRAM):
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sdram_module.timing_settings)
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sdram_module.timing_settings)
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self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
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self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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self.add_csr("ethphy")
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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