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soc/cores/gpio: remove intermediate _pads signal.
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1 changed files with 1 additions and 4 deletions
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@ -53,12 +53,9 @@ class GPIOTristate(Module, AutoCSR):
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# # #
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_pads = Signal(nbits)
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self.comb += _pads.eq(pads)
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for i in range(nbits):
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t = TSTriple()
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self.specials += t.get_tristate(_pads[i])
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self.specials += t.get_tristate(pads[i])
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self.comb += t.oe.eq(self._oe.storage[i])
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self.comb += t.o.eq(self._out.storage[i])
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self.specials += MultiReg(t.i, self._in.status[i])
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