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mibuild/altera_quartus: add support for verilog include
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parent
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commit
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1 changed files with 5 additions and 2 deletions
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@ -47,11 +47,14 @@ def _build_qsf(named_sc, named_pc):
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r += "\n" + "\n\n".join(named_pc)
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return r
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def _build_files(device, sources, named_sc, named_pc, build_name):
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def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
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qsf_contents = ""
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for filename, language in sources:
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qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"
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for path in vincpaths:
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qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\","/") + "\n"
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qsf_contents += _build_qsf(named_sc, named_pc)
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qsf_contents += "set_global_assignment -name DEVICE " + device
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tools.write_to_file(build_name + ".qsf", qsf_contents)
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@ -86,7 +89,7 @@ class AlteraQuartusPlatform(GenericPlatform):
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v_file = build_name + ".v"
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tools.write_to_file(v_file, v_src)
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sources = self.sources + [(v_file, "verilog")]
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_build_files(self.device, sources, named_sc, named_pc, build_name)
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_build_files(self.device, sources, self.verilog_include_paths, named_sc, named_pc, build_name)
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if run:
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_run_quartus(build_name, quartus_path)
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