liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
- rename ft2232h phy to ft245. - make crc optional - fix depacketizer - refactor uart (it's now only a wrapper around standard UART) - fix and update dma
This commit is contained in:
Florent Kermarrec
parent
8aa3fb3eb7
commit
603b4cdc8c
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@ -3,6 +3,7 @@ from migen.genlib.fsm import *
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from migen.actorlib.fifo import *
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from migen.flow.actor import EndpointDescription
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from migen.actorlib.packet import *
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from migen.actorlib.structuring import Pipeline
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packet_header_length = 9
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@ -49,11 +50,12 @@ class LiteUSBMasterPort:
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class LiteUSBSlavePort:
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def __init__(self, dw):
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def __init__(self, dw, tag):
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self.sink = Sink(user_description(dw))
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self.source = Source(user_description(dw))
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self.tag = tag
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class LiteUSBUserPort(LiteUSBSlavePort):
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def __init__(self, dw):
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LiteUSBSlavePort.__init__(self, dw)
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def __init__(self, dw, tag):
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LiteUSBSlavePort.__init__(self, dw, tag)
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@ -3,29 +3,29 @@ from misoclib.com.liteusb.core.packet import LiteUSBPacketizer, LiteUSBDepacketi
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from misoclib.com.liteusb.core.crc import LiteUSBCRC32Inserter, LiteUSBCRC32Checker
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from misoclib.com.liteusb.core.crossbar import LiteUSBCrossbar
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# XXX Header should be protected by CRC
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class LiteUSBCore(Module):
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def __init__(self, phy):
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def __init__(self, phy, clk_freq, with_crc=True):
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rx_pipeline = [phy]
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tx_pipeline = [phy]
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# depacketizer / packetizer
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self.submodules.depacketizer = LiteUSBDepacketizer()
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self.submodules.depacketizer = LiteUSBDepacketizer(clk_freq)
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self.submodules.packetizer = LiteUSBPacketizer()
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self.comb += [
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Record.connect(phy.source, self.depacketizer.sink),
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Record.connect(self.packetizer.source, phy.sink)
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]
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rx_pipeline += [self.depacketizer]
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tx_pipeline += [self.packetizer]
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# crc checker / inserter
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self.submodules.crc_rx = LiteUSBCRC32Checker()
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self.submodules.crc_tx = LiteUSBCRC32Inserter()
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self.comb += [
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Record.connect(self.depacketizer.source, self.crc_rx.sink),
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Record.connect(self.crc_tx.source, self.packetizer.sink)
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]
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if with_crc:
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# crc checker / inserter
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self.submodules.crc_rx = LiteUSBCRC32Checker()
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self.submodules.crc_tx = LiteUSBCRC32Inserter()
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rx_pipeline += [self.crc_rx]
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tx_pipeline += [self.crc_tx]
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# crossbar
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# crossbar
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self.submodules.crossbar = LiteUSBCrossbar()
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self.comb += [
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Record.connect(self.crossbar.master.source, self.crc_tx.sink),
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Record.connect(self.crc_rx.source, self.crossbar.master.sink)
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]
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rx_pipeline += [self.crossbar.master]
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tx_pipeline += [self.crossbar.master]
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# graph
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self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
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self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
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@ -9,7 +9,7 @@ class LiteUSBCrossbar(Module):
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self.dispatch_param = "dst"
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def get_port(self, dst):
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port = LiteUSBUserPort(8)
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port = LiteUSBUserPort(8, dst)
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if dst in self.users.keys():
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raise ValueError("Destination {0:#x} already assigned".format(dst))
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self.users[dst] = port
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@ -66,7 +66,7 @@ class LiteUSBPacketizer(Module):
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class LiteUSBDepacketizer(Module):
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def __init__(self, timeout=10):
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def __init__(self, clk_freq, timeout=10):
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self.sink = sink = Sink(phy_description(8))
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self.source = source = Source(user_description(8))
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@ -116,9 +116,9 @@ class LiteUSBDepacketizer(Module):
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header_pack.source.ack.eq(1),
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)
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self.submodules.timeout = Timeout(60000000*timeout) #XXX use clk_freq
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self.submodules.timeout = Timeout(clk_freq*timeout)
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self.comb += [
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self.timeout.reset.eq(fsm.ongoing("WAIT_SOP")),
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self.timeout.reset.eq(fsm.ongoing("IDLE")),
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self.timeout.ce.eq(1)
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]
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@ -16,7 +16,7 @@ class LiteUSBDMAWriter(Module, AutoCSR):
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# Pack data
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pack_factor = lasmim.dw//8
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pack = structuring.Pack(phy_layout, pack_factor, reverse=True)
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pack = structuring.Pack(phy_description(8), pack_factor, reverse=True)
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cast = structuring.Cast(pack.source.payload.layout, lasmim.dw)
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# DMA
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@ -61,12 +61,12 @@ class LiteUSBDMAReader(Module, AutoCSR):
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pack_factor = lasmim.dw//8
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packed_dat = structuring.pack_layout(8, pack_factor)
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cast = structuring.Cast(lasmim.dw, packed_dat)
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unpack = structuring.Unpack(pack_factor, phy_layout, reverse=True)
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unpack = structuring.Unpack(pack_factor, phy_description(8), reverse=True)
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# Graph
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cnt = Signal(32)
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self.sync += \
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If(self.dma.generator._r_shoot.re,
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If(self.dma.generator._shoot.re,
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cnt.eq(0)
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).Elif(source.stb & source.ack,
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cnt.eq(cnt + 1)
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@ -92,12 +92,11 @@ class LiteUSBDMAReader(Module, AutoCSR):
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class LiteUSBDMA(Module, AutoCSR):
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def __init__(self, lasmim_dma_wr, lasmim_dma_rd, tag):
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self.tag = tag
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def __init__(self, port, lasmim_dma_wr, lasmim_dma_rd):
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self.submodules.writer = LiteUSBDMAWriter(lasmim_dma_wr)
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self.submodules.reader = LiteUSBDMAReader(lasmim_dma_rd, self.tag)
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self.submodules.reader = LiteUSBDMAReader(lasmim_dma_rd, port.tag)
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self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
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self.sink = self.writer.sink
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self.source = self.reader.source
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self.comb += [
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Record.connect(port.source, self.writer.sink),
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Record.connect(self.reader.source, port.sink),
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]
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@ -1,59 +1,35 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.actorlib.fifo import SyncFIFO
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from misoclib.com.liteusb.common import *
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from misoclib.com.uart import UART
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class LiteUSBUARTPHY:
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def __init__(self):
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self.sink = Sink([("data", 8)])
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self.source = Source([("data", 8)])
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class LiteUSBUART(Module, AutoCSR):
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def __init__(self, tag, fifo_depth=64):
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self.tag = tag
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class LiteUSBUART(UART):
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def __init__(self, port,
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tx_fifo_depth=16,
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rx_fifo_depth=16):
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self._rxtx = CSR(8)
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourcePulse()
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self.ev.rx = EventSourceLevel()
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self.ev.finalize()
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self.source = source = Source(user_description(8))
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self.sink = sink = Sink(user_description(8))
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# # #
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phy = LiteUSBUARTPHY()
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UART.__init__(self, phy, tx_fifo_depth, rx_fifo_depth)
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# TX
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tx_start = self._rxtx.re
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tx_done = self.ev.tx.trigger
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self.sync += \
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If(tx_start,
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source.stb.eq(1),
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source.data.eq(self._rxtx.r),
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).Elif(tx_done,
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source.stb.eq(0)
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)
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self.comb += [
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source.sop.eq(1),
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source.eop.eq(1),
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source.length.eq(1),
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source.dst.eq(self.tag),
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tx_done.eq(source.stb & source.ack),
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port.sink.stb.eq(phy.sink.stb),
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port.sink.sop.eq(1),
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port.sink.eop.eq(1),
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port.sink.length.eq(1),
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port.sink.dst.eq(port.tag),
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port.sink.data.eq(phy.sink.data),
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phy.sink.ack.eq(port.sink.ack)
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]
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# RX
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rx_available = self.ev.rx.trigger
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rx_fifo = SyncFIFO(8, fifo_depth)
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self.submodules += rx_fifo
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self.comb += [
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Record.connect(sink, rx_fifo.sink),
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rx_fifo.we.eq(sink.stb),
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sink.ack.eq(sink.stb & rx_fifo.writable),
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rx_fifo.din.eq(sink.data),
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rx_available.eq(rx_fifo.stb),
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rx_fifo.ack.eq(self.ev.rx.clear),
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self._rxtx.w.eq(rx_fifo.dout)
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phy.source.stb.eq(port.source.stb),
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phy.source.data.eq(port.source.data),
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port.source.ack.eq(phy.source.ack)
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]
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@ -1,3 +1,5 @@
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import math
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from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
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@ -24,39 +26,31 @@ def anti_starvation(module, timeout):
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return en, max_time
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class FT2232HPHYSynchronous(Module):
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def __init__(self, pads,
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class FT245PHYSynchronous(Module):
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def __init__(self, pads, clk_freq,
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fifo_depth=32,
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read_time=16,
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write_time=16):
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read_time=128,
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write_time=128):
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dw = flen(pads.data)
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#
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# Read / Write Fifos
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#
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# Read Fifo (Ftdi --> SoC)
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# read fifo (FTDI --> SoC)
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read_fifo = RenameClockDomains(AsyncFIFO(phy_description(8), fifo_depth),
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{"write": "ftdi", "read": "sys"})
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read_buffer = RenameClockDomains(SyncFIFO(phy_description(8), 4),
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{"sys": "ftdi"})
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self.comb += read_buffer.source.connect(read_fifo.sink)
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# Write Fifo (SoC --> Ftdi)
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# write fifo (SoC --> FTDI)
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write_fifo = RenameClockDomains(AsyncFIFO(phy_description(8), fifo_depth),
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{"write": "sys", "read": "ftdi"})
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self.submodules += read_fifo, read_buffer, write_fifo
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#
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# Sink / Source interfaces
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#
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# sink / source interfaces
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self.sink = write_fifo.sink
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self.source = read_fifo.source
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#
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# Read / Write Arbitration
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#
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# read / write arbitration
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wants_write = Signal()
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wants_read = Signal()
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@ -102,14 +96,13 @@ class FT2232HPHYSynchronous(Module):
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NextState("READ")
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)
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#
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# Read / Write Actions
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#
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# databus tristate
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data_w = Signal(dw)
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data_r = Signal(dw)
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data_oe = Signal()
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self.specials += Tristate(pads.data, data_w, data_oe, data_r)
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# read / write actions
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pads.oe_n.reset = 1
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pads.rd_n.reset = 1
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pads.wr_n.reset = 1
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@ -145,43 +138,35 @@ class FT2232HPHYSynchronous(Module):
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)
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]
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#
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# Databus Tristate
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#
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self.specials += Tristate(pads.data, data_w, data_oe, data_r)
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self.debug = Signal(8)
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self.comb += self.debug.eq(data_r)
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class FT2232HPHYAsynchronous(Module):
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class FT245PHYAsynchronous(Module):
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def __init__(self, pads, clk_freq,
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fifo_depth=32,
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read_time=16,
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write_time=16):
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read_time=128,
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write_time=128):
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dw = flen(pads.data)
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self.clk_freq = clk_freq
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#
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# Read / Write Fifos
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#
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# timings
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tRD = self.ns(30) # RD# active pulse width (t4)
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tRDDataSetup = self.ns(14) # RD# to DATA (t3)
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tWRDataSetup = self.ns(5) # DATA to WR# active setup time (t8)
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tWR = self.ns(30) # WR# active pulse width (t10)
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tMultiReg = 2
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# Read Fifo (Ftdi --> SoC)
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# read fifo (FTDI --> SoC)
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read_fifo = SyncFIFO(phy_description(8), fifo_depth)
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# Write Fifo (SoC --> Ftdi)
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# write fifo (SoC --> FTDI)
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write_fifo = SyncFIFO(phy_description(8), fifo_depth)
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self.submodules += read_fifo, write_fifo
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#
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# Sink / Source interfaces
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#
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# sink / source interfaces
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self.sink = write_fifo.sink
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self.source = read_fifo.source
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#
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# Read / Write Arbitration
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#
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# read / write arbitration
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wants_write = Signal()
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wants_read = Signal()
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@ -233,9 +218,7 @@ class FT2232HPHYAsynchronous(Module):
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NextState("READ")
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)
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#
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# Databus Tristate
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#
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# databus tristate
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data_w = Signal(dw)
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data_r_async = Signal(dw)
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data_r = Signal(dw)
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@ -245,10 +228,8 @@ class FT2232HPHYAsynchronous(Module):
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MultiReg(data_r_async, data_r)
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]
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#
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# Read / Write Actions
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#
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pads.wr_n.reset = 1
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# read actions
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pads.rd_n.reset = 1
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read_fsm = FSM(reset_state="IDLE")
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@ -267,7 +248,7 @@ class FT2232HPHYAsynchronous(Module):
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read_fsm.act("PULSE_RD_N",
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pads.rd_n.eq(0),
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read_counter.ce.eq(1),
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If(read_counter.value == 15, # XXX Compute exact value
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If(read_counter.value == max((tRD-1), (tRDDataSetup + tMultiReg -1)),
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NextState("ACQUIRE_DATA")
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)
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)
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@ -282,6 +263,9 @@ class FT2232HPHYAsynchronous(Module):
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)
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)
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# write actions
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pads.wr_n.reset = 1
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write_fsm = FSM(reset_state="IDLE")
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write_counter = Counter(8)
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self.submodules += write_fsm, write_counter
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@ -299,7 +283,7 @@ class FT2232HPHYAsynchronous(Module):
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data_oe.eq(1),
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data_w.eq(write_fifo.source.data),
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write_counter.ce.eq(1),
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If(write_counter.value == 5, # XXX Compute exact value
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If(write_counter.value == (tWRDataSetup-1),
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write_counter.reset.eq(1),
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NextState("PULSE_WR_N")
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)
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@ -309,7 +293,7 @@ class FT2232HPHYAsynchronous(Module):
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data_w.eq(write_fifo.source.data),
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pads.wr_n.eq(0),
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write_counter.ce.eq(1),
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If(write_counter.value == 15, # XXX Compute exact value
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If(write_counter.value == (tWR-1),
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NextState("WAIT_TXE_N")
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)
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)
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@ -319,3 +303,17 @@ class FT2232HPHYAsynchronous(Module):
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NextState("IDLE")
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)
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)
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def ns(self, t, margin=True):
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clk_period_ns = 1000000000/self.clk_freq
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if margin:
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t += clk_period_ns/2
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return math.ceil(t/clk_period_ns)
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def FT245PHY(pads, *args, **kwargs):
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# autodetect PHY
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if hasattr(pads, "oe_n"):
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return FT245PHYSynchronous(pads, *args, **kwargs)
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else:
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return FT245PHYAsynchronous(pads, *args, **kwargs)
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@ -3,11 +3,11 @@ PYTHON = python3
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CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)
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||||
|
||||
ft2232h_sync_tb:
|
||||
$(CMD) ft2232h_sync_tb.py
|
||||
ft245_sync_tb:
|
||||
$(CMD) ft245_sync_tb.py
|
||||
|
||||
ft2232h_async_tb:
|
||||
$(CMD) ft2232h_async_tb.py
|
||||
ft245_async_tb:
|
||||
$(CMD) ft245_async_tb.py
|
||||
|
||||
core_tb:
|
||||
$(CMD) core_tb.py
|
||||
|
|
|
|||
|
|
@ -5,18 +5,22 @@ from migen.fhdl.specials import *
|
|||
from migen.sim.generic import run_simulation
|
||||
|
||||
from misoclib.com.liteusb.common import *
|
||||
from misoclib.com.liteusb.phy.ft2232h import FT2232HPHYAsynchronous
|
||||
from misoclib.com.liteusb.phy.ft245 import FT245PHYAsynchronous
|
||||
from misoclib.com.liteusb.test.common import *
|
||||
|
||||
# XXX for now use it from liteeth to avoid duplication
|
||||
from misoclib.com.liteeth.test.common import *
|
||||
|
||||
class FT2232HAsynchronousModel(Module, RandRun):
|
||||
def __init__(self, rd_data):
|
||||
RandRun.__init__(self, 10)
|
||||
class FT245AsynchronousModel(Module):
|
||||
def __init__(self, clk_freq, rd_data):
|
||||
self.clk_freq = clk_freq
|
||||
self.rd_data = [0] + rd_data
|
||||
self.rd_idx = 0
|
||||
|
||||
# timings
|
||||
self.tRDInactive = self.ns(49) # RXF# inactive after RD# cycle
|
||||
self.tWRInactive = self.ns(49) # TXE# inactive after WR# cycle
|
||||
|
||||
# pads
|
||||
self.data = Signal(8)
|
||||
self.rxf_n = Signal(reset=1)
|
||||
|
|
@ -48,11 +52,10 @@ class FT2232HAsynchronousModel(Module, RandRun):
|
|||
else:
|
||||
if (not selfp.wr_n and self.last_wr_n) and not selfp.txe_n:
|
||||
self.wr_data.append(selfp.data_w)
|
||||
self.wr_delay = 20 # XXX FIXME
|
||||
self.wr_delay = self.tWRInactive
|
||||
self.last_wr_n = selfp.wr_n
|
||||
|
||||
if self.run:
|
||||
selfp.txe_n = 0
|
||||
selfp.txe_n = 0
|
||||
|
||||
def rd_sim(self, selfp):
|
||||
if self.rd_delay:
|
||||
|
|
@ -60,12 +63,9 @@ class FT2232HAsynchronousModel(Module, RandRun):
|
|||
self.rd_delay = self.rd_delay - 1
|
||||
else:
|
||||
rxf_n = selfp.rxf_n
|
||||
if self.run:
|
||||
if self.rd_idx < len(self.rd_data)-1:
|
||||
self.rd_done = selfp.rxf_n
|
||||
selfp.rxf_n = 0
|
||||
else:
|
||||
selfp.rxf_n = self.rd_done
|
||||
if self.rd_idx < len(self.rd_data)-1:
|
||||
self.rd_done = selfp.rxf_n
|
||||
selfp.rxf_n = 0
|
||||
else:
|
||||
selfp.rxf_n = self.rd_done
|
||||
|
||||
|
|
@ -75,12 +75,11 @@ class FT2232HAsynchronousModel(Module, RandRun):
|
|||
selfp.data_r = self.rd_data[self.rd_idx]
|
||||
self.rd_done = 1
|
||||
if selfp.rd_n and not self.last_rd_n:
|
||||
self.rd_delay = 4 # XXX FIXME
|
||||
self.rd_delay = self.tRDInactive
|
||||
|
||||
self.last_rd_n = selfp.rd_n
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
RandRun.do_simulation(self, selfp)
|
||||
if self.init:
|
||||
selfp.rxf_n = 0
|
||||
self.wr_data = []
|
||||
|
|
@ -88,13 +87,21 @@ class FT2232HAsynchronousModel(Module, RandRun):
|
|||
self.wr_sim(selfp)
|
||||
self.rd_sim(selfp)
|
||||
|
||||
def ns(self, t, margin=True):
|
||||
clk_period_ns = 1000000000/self.clk_freq
|
||||
if margin:
|
||||
t += clk_period_ns/2
|
||||
return math.ceil(t/clk_period_ns)
|
||||
|
||||
|
||||
test_packet = [i%256 for i in range(128)]
|
||||
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.model = FT2232HAsynchronousModel(test_packet)
|
||||
self.submodules.phy = FT2232HPHYAsynchronous(self.model, 50000000)
|
||||
clk_freq = 50*1000000
|
||||
self.submodules.model = FT245AsynchronousModel(clk_freq, test_packet)
|
||||
self.submodules.phy = FT245PHYAsynchronous(self.model, clk_freq)
|
||||
|
||||
self.submodules.streamer = PacketStreamer(phy_description(8))
|
||||
self.submodules.streamer_randomizer = AckRandomizer(phy_description(8), level=10)
|
||||
|
|
@ -5,13 +5,13 @@ from migen.fhdl.specials import *
|
|||
from migen.sim.generic import run_simulation
|
||||
|
||||
from misoclib.com.liteusb.common import *
|
||||
from misoclib.com.liteusb.phy.ft2232h import FT2232HPHYSynchronous
|
||||
from misoclib.com.liteusb.phy.ft245 import FT245PHYSynchronous
|
||||
from misoclib.com.liteusb.test.common import *
|
||||
|
||||
# XXX for now use it from liteeth to avoid duplication
|
||||
from misoclib.com.liteeth.test.common import *
|
||||
|
||||
class FT2232HSynchronousModel(Module, RandRun):
|
||||
class FT245SynchronousModel(Module, RandRun):
|
||||
def __init__(self, rd_data):
|
||||
RandRun.__init__(self, 10)
|
||||
self.rd_data = [0] + rd_data
|
||||
|
|
@ -82,8 +82,8 @@ test_packet = [i%256 for i in range(512)]
|
|||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.model = FT2232HSynchronousModel(test_packet)
|
||||
self.submodules.phy = FT2232HPHYSynchronous(self.model)
|
||||
self.submodules.model = FT245SynchronousModel(test_packet)
|
||||
self.submodules.phy = FT245PHYSynchronous(self.model)
|
||||
|
||||
self.submodules.streamer = PacketStreamer(phy_description(8))
|
||||
self.submodules.streamer_randomizer = AckRandomizer(phy_description(8), level=10)
|
||||
Loading…
Reference in New Issue