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soc/cores/clock/ECP5PLL: add CLKI_DIV support.

This commit is contained in:
Florent Kermarrec 2020-04-03 11:14:57 +02:00
parent 27f00851d0
commit 6043108376
1 changed files with 28 additions and 26 deletions
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8
litex/soc/cores/clock.py
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@ -598,6 +598,7 @@ class iCE40PLL(Module):
class ECP5PLL(Module): class ECP5PLL(Module):
nclkouts_max = 3 nclkouts_max = 3
clki_div_range = (1, 128+1)
clkfb_div_range = (1, 128+1) clkfb_div_range = (1, 128+1)
clko_div_range = (1, 128+1) clko_div_range = (1, 128+1)
clki_freq_range = ( 8e6, 400e6) clki_freq_range = ( 8e6, 400e6)
@ -641,10 +642,11 @@ class ECP5PLL(Module):
def compute_config(self): def compute_config(self):
config = {} config = {}
config["clki_div"] = 1 for clki_div in range(*self.clki_div_range):
config["clki_div"] = clki_div
for clkfb_div in range(*self.clkfb_div_range): for clkfb_div in range(*self.clkfb_div_range):
all_valid = True all_valid = True
vco_freq = self.clkin_freq*clkfb_div*1 # clkos3_div=1 vco_freq = self.clkin_freq/clki_div*clkfb_div*1 # clkos3_div=1
(vco_freq_min, vco_freq_max) = self.vco_freq_range (vco_freq_min, vco_freq_max) = self.vco_freq_range
if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max: if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
for n, (clk, f, p, m) in sorted(self.clkouts.items()): for n, (clk, f, p, m) in sorted(self.clkouts.items()):
@ -684,7 +686,7 @@ class ECP5PLL(Module):
p_CLKOS3_ENABLE = "ENABLED", p_CLKOS3_ENABLE = "ENABLED",
p_CLKOS3_DIV = 1, p_CLKOS3_DIV = 1,
p_CLKFB_DIV = config["clkfb_div"], p_CLKFB_DIV = config["clkfb_div"],
p_CLKI_DIV = 1, p_CLKI_DIV = config["clki_div"],
) )
for n, (clk, f, p, m) in sorted(self.clkouts.items()): for n, (clk, f, p, m) in sorted(self.clkouts.items()):
n_to_l = {0: "P", 1: "S", 2: "S2"} n_to_l = {0: "P", 1: "S", 2: "S2"}