soc/cores/clock/ECP5PLL: add CLKI_DIV support.
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27f00851d0
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@ -598,6 +598,7 @@ class iCE40PLL(Module):
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class ECP5PLL(Module):
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nclkouts_max = 3
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clki_div_range = (1, 128+1)
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clkfb_div_range = (1, 128+1)
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clko_div_range = (1, 128+1)
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clki_freq_range = ( 8e6, 400e6)
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@ -641,10 +642,11 @@ class ECP5PLL(Module):
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def compute_config(self):
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config = {}
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config["clki_div"] = 1
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for clki_div in range(*self.clki_div_range):
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config["clki_div"] = clki_div
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for clkfb_div in range(*self.clkfb_div_range):
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all_valid = True
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vco_freq = self.clkin_freq*clkfb_div*1 # clkos3_div=1
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vco_freq = self.clkin_freq/clki_div*clkfb_div*1 # clkos3_div=1
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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@ -684,7 +686,7 @@ class ECP5PLL(Module):
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p_CLKOS3_ENABLE = "ENABLED",
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p_CLKOS3_DIV = 1,
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p_CLKFB_DIV = config["clkfb_div"],
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p_CLKI_DIV = 1,
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p_CLKI_DIV = config["clki_div"],
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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n_to_l = {0: "P", 1: "S", 2: "S2"}
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