build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts.
nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper. We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
This commit is contained in:
Florent Kermarrec
parent
2243f628f7
commit
6048a5291c
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@ -12,8 +12,8 @@ from litex.build.lattice import common
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# TODO:
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# - add timing constraint support.
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# - add inout support to iowrapper.
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# - check/document attr_translate.
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# - use constraint file when prjtrellis will support it.
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nextpnr_ecp5_architectures = {
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@ -40,21 +40,22 @@ def yosys_import_sources(platform):
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return "\n".join(reads)
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def generate_prjtrellis_iowrapper(platform, vns):
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def generate_prjtrellis_top(top_file, platform, vns):
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# resolve ios directions / types
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ios, _ = platform.resolve_signals(vns)
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ios_direction = {}
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# resolve ios directions
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ios_type = {}
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cm = platform.constraint_manager
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for io_name, io_pins, _, _ in ios:
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for cm_sig, cm_pins, _, _ in cm.get_sig_constraints():
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if io_pins == cm_pins:
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ios_direction[io_name] = cm_sig.direction
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ios_type[io_name] = cm_sig.type
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last_io_name = io_name
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iowrapper_contents = []
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iowrapper_contents.append("module {build_name}_iowrapper(")
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# ios declaration
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# prjtrellis module / ios declaration
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top_contents = []
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top_contents.append("module prjtrellis_{build_name}(")
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ios_declaration = ""
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for io_name, io_pins, io_others, _ in ios:
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for io_other in io_others:
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@ -64,20 +65,20 @@ def generate_prjtrellis_iowrapper(platform, vns):
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ios_declaration += "(* LOC=\"{}\" *) (* IO_TYPE=\"{}\" *)\n".format(io_pin, io_standard)
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ios_declaration += "\t" + ios_direction[io_name] + " " + io_name + "_io" + (str(i) if len(io_pins) > 1 else "")
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ios_declaration += ",\n" if io_name != last_io_name or (i != len(io_pins) - 1) else ""
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iowrapper_contents.append(ios_declaration)
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iowrapper_contents.append(");\n")
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top_contents.append(ios_declaration)
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top_contents.append(");\n")
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# wires declaration
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wires_declaration = ""
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# top signals declaration
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signals_declaration = ""
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for io_name, io_pins, _, _ in ios:
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wires_declaration += "wire "
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signals_declaration += ios_type[io_name] + " "
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if len(io_pins) > 1:
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wires_declaration += "[{}:0] ".format(len(io_pins) - 1)
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wires_declaration += io_name
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wires_declaration += ";\n"
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iowrapper_contents.append(wires_declaration)
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signals_declaration += "[{}:0] ".format(len(io_pins) - 1)
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signals_declaration += io_name
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signals_declaration += ";\n"
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top_contents.append(signals_declaration)
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# trellis_io declaration
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# trellis_ios declaration
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trellis_io_declaration = ""
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for io_name, io_pins, io_others, _ in ios:
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for i, io_pin in enumerate(io_pins):
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@ -92,30 +93,38 @@ def generate_prjtrellis_iowrapper(platform, vns):
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io_name + "_buf" + str(i), io_name + "_" + io_suffix, io_name + "[" + str(i) + "]")
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else:
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pass # handled by Migen's Tristate
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iowrapper_contents.append(trellis_io_declaration)
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top_contents.append(trellis_io_declaration)
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# top declaration
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top_declaration = "{build_name} _{build_name}(\n"
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for io_name, io_pins, _, _ in ios:
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if ios_direction[io_name] == "inout":
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if len(io_pins) > 1:
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io_concat_name = "{{"
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io_concat_name += ",".join([io_name + "_io" + str(i) for i in range(len(io_pins))])
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io_concat_name += "}}"
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top_declaration += "\t." + io_name + "(" + io_concat_name + ")"
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else:
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top_declaration += "\t." + io_name + "(" + io_name + "_io)"
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else:
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top_declaration += "\t." + io_name + "(" + io_name + ")"
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top_declaration += ",\n" if io_name != last_io_name else "\n"
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top_declaration += ");\n"
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iowrapper_contents.append(top_declaration)
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# top_recopy:
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# - skip module definition.
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# - use ios names for inouts.
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def replace_inouts(l):
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r = l
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for io_name, io_pins, _, _ in ios:
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if ios_direction[io_name] == "inout":
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if len(io_pins) > 1:
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for i in range(len(io_pins)):
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r = r.replace(io_name + "[" + str(i) + "]", io_name + "_io" + str(i))
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else:
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r = r.replace(io_name, io_name + "_io")
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return r
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iowrapper_contents.append("endmodule")
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skip = True
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f = open(top_file, "r")
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for l in f:
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if not skip:
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l = l.replace("\n", "")
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l = l.replace("{", "{{")
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l = l.replace("}", "}}")
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l = replace_inouts(l)
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top_contents.append(l)
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if ");" in l:
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skip = False
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f.close()
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iowrapper_contents = "\n".join(iowrapper_contents)
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top_contents = "\n".join(top_contents)
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return iowrapper_contents
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return top_contents
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class LatticePrjTrellisToolchain:
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@ -147,24 +156,22 @@ class LatticePrjTrellisToolchain:
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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v_output = platform.get_verilog(fragment)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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top_output = platform.get_verilog(fragment)
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top_file = build_name + ".v"
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top_output.write(top_file)
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# generate iowrapper (with constraints and trellis_ios)
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# FIXME: remove when prjtrellis will support constraint files
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iowrapper_file = build_name + "_iowrapper.v"
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iowrapper_contents = generate_prjtrellis_iowrapper(platform, v_output.ns)
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iowrapper_contents = iowrapper_contents.format(build_name=build_name)
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tools.write_to_file(iowrapper_file, iowrapper_contents)
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platform.add_source(iowrapper_file)
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# insert constraints and trellis_io to generated verilog
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prjtrellis_top_file = build_name + "_prjtrellis.v"
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prjtrellis_top_contents = generate_prjtrellis_top(top_file, platform, top_output.ns)
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prjtrellis_top_contents = prjtrellis_top_contents.format(build_name=build_name)
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tools.write_to_file(prjtrellis_top_file, prjtrellis_top_contents)
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platform.add_source(prjtrellis_top_file)
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# generate yosys script
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yosys_script_file = build_name + ".ys"
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yosys_script_contents = [
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yosys_import_sources(platform),
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"synth_ecp5 -nomux -json {build_name}.json -top {build_name}_iowrapper"
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"synth_ecp5 -nomux -json {build_name}.json -top prjtrellis_{build_name}"
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]
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yosys_script_contents = "\n".join(yosys_script_contents)
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yosys_script_contents = yosys_script_contents.format(build_name=build_name)
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@ -206,6 +206,7 @@ def _printheader(f, ios, name, ns, attr_translate,
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attr = _printattr(sig.attr, attr_translate)
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if attr:
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r += "\t" + attr
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sig.type = "wire"
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if sig in inouts:
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sig.direction = "inout"
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r += "\tinout " + _printsig(ns, sig)
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@ -214,6 +215,7 @@ def _printheader(f, ios, name, ns, attr_translate,
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if sig in wires:
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r += "\toutput " + _printsig(ns, sig)
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else:
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sig.type = "reg"
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r += "\toutput reg " + _printsig(ns, sig)
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else:
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sig.direction = "input"
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